609 lines
18 KiB
C++
609 lines
18 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: acpi.cc,v 1.14 2008-03-26 16:25:05 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2006 Volker Ruppert
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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// PIIX4 ACPI support
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//
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "bochs.h"
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#include "iodev.h"
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#if BX_SUPPORT_PCI && BX_SUPPORT_ACPI
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#define LOG_THIS theACPIController->
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bx_acpi_ctrl_c* theACPIController = NULL;
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// FIXME
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const Bit8u acpi_pm_iomask[64] = {2, 0, 2, 0, 2, 0, 0, 0, 4, 0, 0, 0, 7, 7, 7, 7,
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7, 7, 7, 7, 1, 1, 0, 0, 7, 7, 0, 0, 7, 7, 7, 7,
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7, 7, 0, 0, 0, 0, 0, 0, 7, 7, 7, 7, 7, 7, 7, 7,
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1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0};
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const Bit8u acpi_sm_iomask[16] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 0, 2, 0, 0, 0};
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#define PM_FREQ 3579545
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#define ACPI_DBG_IO_ADDR 0xb044
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define SCI_EN (1 << 0)
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#define SUS_EN (1 << 13)
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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extern void apic_bus_deliver_smi(void);
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int libacpi_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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theACPIController = new bx_acpi_ctrl_c();
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bx_devices.pluginACPIController = theACPIController;
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, theACPIController, BX_PLUGIN_ACPI);
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return 0; // Success
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}
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void libacpi_LTX_plugin_fini(void)
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{
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delete theACPIController;
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}
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/* ported from QEMU: compute with 96 bit intermediate result: (a*b)/c */
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Bit64u muldiv64(Bit64u a, Bit32u b, Bit32u c)
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{
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union {
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Bit64u ll;
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struct {
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#ifdef WORDS_BIGENDIAN
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Bit32u high, low;
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#else
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Bit32u low, high;
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#endif
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} l;
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} u, res;
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Bit64u rl, rh;
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u.ll = a;
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rl = (Bit64u)u.l.low * (Bit64u)b;
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rh = (Bit64u)u.l.high * (Bit64u)b;
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rh += (rl >> 32);
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res.l.high = (Bit32u)(rh / c);
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res.l.low = (Bit32u)(((rh % c) << 32) + (rl & 0xffffffff)) / c;
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return res.ll;
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}
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bx_acpi_ctrl_c::bx_acpi_ctrl_c()
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{
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put("ACPI");
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settype(ACPILOG);
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s.timer_index = BX_NULL_TIMER_HANDLE;
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}
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bx_acpi_ctrl_c::~bx_acpi_ctrl_c()
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{
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BX_DEBUG(("Exit"));
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}
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void bx_acpi_ctrl_c::init(void)
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{
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// called once when bochs initializes
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unsigned i;
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BX_ACPI_THIS s.devfunc = BX_PCI_DEVICE(1, 3);
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DEV_register_pci_handlers(this, &BX_ACPI_THIS s.devfunc, BX_PLUGIN_ACPI,
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"ACPI Controller");
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if (BX_ACPI_THIS s.timer_index == BX_NULL_TIMER_HANDLE) {
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BX_ACPI_THIS s.timer_index =
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bx_pc_system.register_timer(this, timer_handler, 1000, 0, 0, "ACPI");
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}
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DEV_register_iowrite_handler(this, write_handler, ACPI_DBG_IO_ADDR, "ACPI", 4);
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for (i=0; i<256; i++) {
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BX_ACPI_THIS s.pci_conf[i] = 0x0;
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}
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BX_ACPI_THIS s.pm_base = 0x0;
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BX_ACPI_THIS s.sm_base = 0x0;
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// readonly registers
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static const struct init_vals_t {
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unsigned addr;
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unsigned char val;
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} init_vals[] = {
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{ 0x00, 0x86 }, { 0x01, 0x80 },
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{ 0x02, 0x13 }, { 0x03, 0x71 },
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{ 0x08, 0x03 }, // revision number
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{ 0x0a, 0x80 }, // other bridge device
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{ 0x0b, 0x06 }, // bridge device
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{ 0x0e, 0x00 }, // header type
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{ 0x3d, BX_PCI_INTA } // interrupt pin #1
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};
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for (i = 0; i < sizeof(init_vals) / sizeof(*init_vals); ++i) {
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BX_ACPI_THIS s.pci_conf[init_vals[i].addr] = init_vals[i].val;
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}
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}
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void bx_acpi_ctrl_c::reset(unsigned type)
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{
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unsigned i;
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static const struct reset_vals_t {
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unsigned addr;
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unsigned char val;
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} reset_vals[] = {
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{ 0x04, 0x00 }, { 0x05, 0x00 }, // command_io + command_mem
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{ 0x06, 0x80 }, { 0x07, 0x02 }, // status_devsel_medium
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{ 0x3c, 0x00 }, // IRQ
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// PM base 0x40 - 0x43
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{ 0x40, 0x01 }, { 0x41, 0x00 },
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{ 0x42, 0x00 }, { 0x43, 0x00 },
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// device resources
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{ 0x5f, 0x90 }, { 0x63, 0x60 },
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{ 0x67, 0x98 },
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// SM base 0x90 - 0x93
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{ 0x90, 0x01 }, { 0x91, 0x00 },
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{ 0x92, 0x00 }, { 0x93, 0x00 }
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};
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for (i = 0; i < sizeof(reset_vals) / sizeof(*reset_vals); ++i) {
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BX_ACPI_THIS s.pci_conf[reset_vals[i].addr] = reset_vals[i].val;
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}
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BX_ACPI_THIS s.pmsts = 0;
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BX_ACPI_THIS s.pmen = 0;
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BX_ACPI_THIS s.pmcntrl = 0;
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BX_ACPI_THIS s.tmr_overflow_time = 0xffffff;
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BX_ACPI_THIS s.smbus.stat = 0;
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BX_ACPI_THIS s.smbus.ctl = 0;
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BX_ACPI_THIS s.smbus.cmd = 0;
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BX_ACPI_THIS s.smbus.addr = 0;
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BX_ACPI_THIS s.smbus.data0 = 0;
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BX_ACPI_THIS s.smbus.data1 = 0;
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BX_ACPI_THIS s.smbus.index = 0;
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for (i = 0; i < 32; i++) {
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BX_ACPI_THIS s.smbus.data[i] = 0;
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}
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}
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void bx_acpi_ctrl_c::register_state(void)
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{
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "acpi", "ACPI Controller State", 6);
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BXRS_HEX_PARAM_FIELD(list, pmsts, BX_ACPI_THIS s.pmsts);
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BXRS_HEX_PARAM_FIELD(list, pmen, BX_ACPI_THIS s.pmen);
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BXRS_HEX_PARAM_FIELD(list, pmcntrl, BX_ACPI_THIS s.pmcntrl);
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BXRS_HEX_PARAM_FIELD(list, tmr_overflow_time, BX_ACPI_THIS s.tmr_overflow_time);
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bx_list_c *smbus = new bx_list_c(list, "smbus", "ACPI SMBus", 8);
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BXRS_HEX_PARAM_FIELD(smbus, stat, BX_ACPI_THIS s.smbus.stat);
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BXRS_HEX_PARAM_FIELD(smbus, ctl, BX_ACPI_THIS s.smbus.ctl);
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BXRS_HEX_PARAM_FIELD(smbus, cmd, BX_ACPI_THIS s.smbus.cmd);
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BXRS_HEX_PARAM_FIELD(smbus, addr, BX_ACPI_THIS s.smbus.addr);
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BXRS_HEX_PARAM_FIELD(smbus, data0, BX_ACPI_THIS s.smbus.data0);
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BXRS_HEX_PARAM_FIELD(smbus, data1, BX_ACPI_THIS s.smbus.data1);
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BXRS_HEX_PARAM_FIELD(smbus, index, BX_ACPI_THIS s.smbus.index);
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bx_list_c *data = new bx_list_c(smbus, "data", "ACPI SMBus data", 32);
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for (unsigned i = 0; i < 32; i++) {
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char name[6];
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sprintf(name, "0x%02x", i);
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new bx_shadow_num_c(data, name, &BX_ACPI_THIS s.smbus.data[i], BASE_HEX);
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}
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register_pci_state(list, BX_ACPI_THIS s.pci_conf);
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}
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void bx_acpi_ctrl_c::after_restore_state(void)
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{
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if (DEV_pci_set_base_io(BX_ACPI_THIS_PTR, read_handler, write_handler,
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&BX_ACPI_THIS s.pm_base,
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&BX_ACPI_THIS s.pci_conf[0x40],
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64, &acpi_pm_iomask[0], "ACPI PM base"))
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{
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BX_INFO(("new PM base address: 0x%04x", BX_ACPI_THIS s.pm_base));
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}
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if (DEV_pci_set_base_io(BX_ACPI_THIS_PTR, read_handler, write_handler,
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&BX_ACPI_THIS s.sm_base,
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&BX_ACPI_THIS s.pci_conf[0x90],
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16, &acpi_sm_iomask[0], "ACPI SM base"))
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{
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BX_INFO(("new SM base address: 0x%04x", BX_ACPI_THIS s.sm_base));
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}
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}
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void bx_acpi_ctrl_c::set_irq_level(bx_bool level)
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{
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DEV_pci_set_irq(BX_ACPI_THIS s.devfunc, BX_ACPI_THIS s.pci_conf[0x3d], level);
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}
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Bit32u bx_acpi_ctrl_c::get_pmtmr(void)
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{
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Bit64u value = muldiv64(bx_pc_system.time_usec(), PM_FREQ, 1000000);
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return (Bit32u)(value & 0xffffff);
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}
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Bit16u bx_acpi_ctrl_c::get_pmsts(void)
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{
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Bit16u pmsts = BX_ACPI_THIS s.pmsts;
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Bit64u value = muldiv64(bx_pc_system.time_usec(), PM_FREQ, 1000000);
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if (value >= BX_ACPI_THIS s.tmr_overflow_time)
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BX_ACPI_THIS s.pmsts |= TMROF_EN;
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return pmsts;
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}
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void bx_acpi_ctrl_c::pm_update_sci(void)
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{
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Bit16u pmsts = get_pmsts();
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bx_bool sci_level = (((pmsts & BX_ACPI_THIS s.pmen) &
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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BX_ACPI_THIS set_irq_level(sci_level);
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// schedule a timer interruption if needed
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if ((BX_ACPI_THIS s.pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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Bit64u expire_time = muldiv64(BX_ACPI_THIS s.tmr_overflow_time, 1000000, PM_FREQ);
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bx_pc_system.activate_timer(BX_ACPI_THIS s.timer_index, (Bit32u)expire_time, 0);
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} else {
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bx_pc_system.deactivate_timer(BX_ACPI_THIS s.timer_index);
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}
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}
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void bx_acpi_ctrl_c::generate_smi(Bit8u value)
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{
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/* ACPI specs 3.0, 4.7.2.5 */
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if (value == ACPI_ENABLE) {
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BX_ACPI_THIS s.pmcntrl |= SCI_EN;
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} else if (value == ACPI_DISABLE) {
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BX_ACPI_THIS s.pmcntrl &= ~SCI_EN;
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}
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if (BX_ACPI_THIS s.pci_conf[0x5b] & 0x02) {
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apic_bus_deliver_smi();
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}
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u bx_acpi_ctrl_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_ACPI_SMF
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bx_acpi_ctrl_c *class_ptr = (bx_acpi_ctrl_c *) this_ptr;
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return class_ptr->read(address, io_len);
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}
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Bit32u bx_acpi_ctrl_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_ACPI_SMF
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Bit8u reg = address & 0x3f;
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Bit32u value = 0xffffffff;
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if ((address & 0xffc0) == BX_ACPI_THIS s.pm_base) {
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if ((BX_ACPI_THIS s.pci_conf[0x80] & 0x01) == 0) {
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return value;
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}
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switch (reg) {
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case 0x00:
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value = BX_ACPI_THIS get_pmsts();
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break;
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case 0x02:
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value = BX_ACPI_THIS s.pmen;
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break;
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case 0x04:
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value = BX_ACPI_THIS s.pmcntrl;
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break;
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case 0x08:
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value = BX_ACPI_THIS get_pmtmr();
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break;
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default:
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BX_INFO(("ACPI read from PM register 0x%02x not implemented yet", reg));
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}
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BX_DEBUG(("ACPI read from PM register 0x%02x returns 0x%08x", reg, value));
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} else {
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if (((BX_ACPI_THIS s.pci_conf[0x04] & 0x01) == 0) &&
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((BX_ACPI_THIS s.pci_conf[0xd2] & 0x01) == 0)) {
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return value;
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}
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switch (reg) {
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case 0x00:
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value = BX_ACPI_THIS s.smbus.stat;
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break;
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case 0x02:
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BX_ACPI_THIS s.smbus.index = 0;
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value = BX_ACPI_THIS s.smbus.ctl & 0x1f;
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break;
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case 0x03:
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value = BX_ACPI_THIS s.smbus.cmd;
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break;
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case 0x04:
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value = BX_ACPI_THIS s.smbus.addr;
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break;
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case 0x05:
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value = BX_ACPI_THIS s.smbus.data0;
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break;
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case 0x06:
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value = BX_ACPI_THIS s.smbus.data1;
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break;
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case 0x07:
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value = BX_ACPI_THIS s.smbus.data[BX_ACPI_THIS s.smbus.index++];
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if (BX_ACPI_THIS s.smbus.index > 31) {
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BX_ACPI_THIS s.smbus.index = 0;
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}
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break;
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default:
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value = 0;
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BX_INFO(("ACPI read from SMBus register 0x%02x not implemented yet", reg));
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}
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BX_DEBUG(("ACPI read from SMBus register 0x%02x returns 0x%08x", reg, value));
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}
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return value;
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void bx_acpi_ctrl_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_ACPI_SMF
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bx_acpi_ctrl_c *class_ptr = (bx_acpi_ctrl_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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void bx_acpi_ctrl_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_ACPI_SMF
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Bit8u reg = address & 0x3f;
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if ((address & 0xffc0) == BX_ACPI_THIS s.pm_base) {
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if ((BX_ACPI_THIS s.pci_conf[0x80] & 0x01) == 0) {
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return;
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}
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BX_DEBUG(("ACPI write to PM register 0x%02x, value = 0x%04x", reg, value));
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switch (reg) {
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case 0x00:
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{
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Bit16u pmsts = BX_ACPI_THIS get_pmsts();
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if (pmsts & value & TMROF_EN) {
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// if TMRSTS is reset, then compute the new overflow time
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Bit64u d = muldiv64(bx_pc_system.time_usec(), PM_FREQ, 1000000);
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BX_ACPI_THIS s.tmr_overflow_time = (d + BX_CONST64(0x800000)) & ~BX_CONST64(0x7fffff);
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}
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BX_ACPI_THIS s.pmsts &= ~value;
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BX_ACPI_THIS pm_update_sci();
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}
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break;
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case 0x02:
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BX_ACPI_THIS s.pmen = value;
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BX_ACPI_THIS pm_update_sci();
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break;
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case 0x04:
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{
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BX_ACPI_THIS s.pmcntrl = value & ~(SUS_EN);
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if (value & SUS_EN) {
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// change suspend type
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Bit16u sus_typ = (value >> 10) & 3;
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switch (sus_typ) {
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case 0: // soft power off
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bx_user_quit = 1;
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LOG_THIS setonoff(LOGLEV_PANIC, ACT_FATAL);
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BX_PANIC(("ACPI control: soft power off"));
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break;
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default:
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break;
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}
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}
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}
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break;
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default:
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BX_INFO(("ACPI write to PM register 0x%02x not implemented yet", reg));
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}
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} else if ((address & 0xfff0) == BX_ACPI_THIS s.sm_base) {
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if (((BX_ACPI_THIS s.pci_conf[0x04] & 0x01) == 0) &&
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((BX_ACPI_THIS s.pci_conf[0xd2] & 0x01) == 0)) {
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return;
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}
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BX_DEBUG(("ACPI write to SMBus register 0x%02x, value = 0x%04x", reg, value));
|
|
switch (reg) {
|
|
case 0x00:
|
|
BX_ACPI_THIS s.smbus.stat = 0;
|
|
BX_ACPI_THIS s.smbus.index = 0;
|
|
break;
|
|
case 0x02:
|
|
BX_ACPI_THIS s.smbus.ctl = 0;
|
|
// TODO: execute SMBus command
|
|
break;
|
|
case 0x03:
|
|
BX_ACPI_THIS s.smbus.cmd = 0;
|
|
break;
|
|
case 0x04:
|
|
BX_ACPI_THIS s.smbus.addr = 0;
|
|
break;
|
|
case 0x05:
|
|
BX_ACPI_THIS s.smbus.data0 = 0;
|
|
break;
|
|
case 0x06:
|
|
BX_ACPI_THIS s.smbus.data1 = 0;
|
|
break;
|
|
case 0x07:
|
|
BX_ACPI_THIS s.smbus.data[BX_ACPI_THIS s.smbus.index++] = value;
|
|
if (BX_ACPI_THIS s.smbus.index > 31) {
|
|
BX_ACPI_THIS s.smbus.index = 0;
|
|
}
|
|
break;
|
|
default:
|
|
BX_INFO(("ACPI write to SMBus register 0x%02x not implemented yet", reg));
|
|
}
|
|
} else {
|
|
BX_DEBUG(("DBG: 0x%08x", value));
|
|
}
|
|
}
|
|
|
|
void bx_acpi_ctrl_c::timer_handler(void *this_ptr)
|
|
{
|
|
bx_acpi_ctrl_c *class_ptr = (bx_acpi_ctrl_c *) this_ptr;
|
|
class_ptr->timer();
|
|
}
|
|
|
|
void bx_acpi_ctrl_c::timer()
|
|
{
|
|
BX_ACPI_THIS pm_update_sci();
|
|
}
|
|
|
|
// pci configuration space read callback handler
|
|
Bit32u bx_acpi_ctrl_c::pci_read_handler(Bit8u address, unsigned io_len)
|
|
{
|
|
Bit32u value = 0;
|
|
|
|
if (io_len > 4 || io_len == 0) {
|
|
BX_DEBUG(("ACPI controller read register 0x%02x, len=%u !",
|
|
(unsigned) address, (unsigned) io_len));
|
|
return 0xffffffff;
|
|
}
|
|
|
|
const char* pszName = " ";
|
|
switch (address) {
|
|
case 0x00: if (io_len == 2) {
|
|
pszName = "(vendor id) ";
|
|
} else if (io_len == 4) {
|
|
pszName = "(vendor + device) ";
|
|
}
|
|
break;
|
|
case 0x04: if (io_len == 2) {
|
|
pszName = "(command) ";
|
|
} else if (io_len == 4) {
|
|
pszName = "(command+status) ";
|
|
}
|
|
break;
|
|
case 0x08: if (io_len == 1) {
|
|
pszName = "(revision id) ";
|
|
} else if (io_len == 4) {
|
|
pszName = "(rev.+class code) ";
|
|
}
|
|
break;
|
|
case 0x0c: pszName = "(cache line size) "; break;
|
|
case 0x28: pszName = "(cardbus cis) "; break;
|
|
case 0x2c: pszName = "(subsys. vendor+) "; break;
|
|
case 0x30: pszName = "(rom base) "; break;
|
|
case 0x3c: pszName = "(interrupt line+) "; break;
|
|
case 0x3d: pszName = "(interrupt pin) "; break;
|
|
}
|
|
|
|
// This odd code is to display only what bytes actually were read.
|
|
char szTmp[9];
|
|
char szTmp2[3];
|
|
szTmp[0] = '\0';
|
|
szTmp2[0] = '\0';
|
|
for (unsigned i=0; i<io_len; i++) {
|
|
value |= (BX_ACPI_THIS s.pci_conf[address+i] << (i*8));
|
|
|
|
sprintf(szTmp2, "%02x", (BX_ACPI_THIS s.pci_conf[address+i]));
|
|
strrev(szTmp2);
|
|
strcat(szTmp, szTmp2);
|
|
}
|
|
strrev(szTmp);
|
|
BX_DEBUG(("ACPI controller read register 0x%02x %svalue 0x%s",
|
|
address, pszName, szTmp));
|
|
return value;
|
|
}
|
|
|
|
|
|
// static pci configuration space write callback handler
|
|
void bx_acpi_ctrl_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
|
|
{
|
|
Bit8u value8, oldval;
|
|
bx_bool pm_base_change = 0, sm_base_change = 0;
|
|
|
|
if ((address >= 0x10) && (address < 0x34))
|
|
return;
|
|
// This odd code is to display only what bytes actually were written.
|
|
char szTmp[9];
|
|
char szTmp2[3];
|
|
szTmp[0] = '\0';
|
|
szTmp2[0] = '\0';
|
|
for (unsigned i=0; i<io_len; i++) {
|
|
value8 = (value >> (i*8)) & 0xFF;
|
|
oldval = BX_ACPI_THIS s.pci_conf[address+i];
|
|
switch (address+i) {
|
|
case 0x04:
|
|
value8 = (value8 & 0xfe) | (value & 0x01);
|
|
goto set_value;
|
|
break;
|
|
case 0x06: // disallowing write to status lo-byte (is that expected?)
|
|
strcpy(szTmp2, "..");
|
|
break;
|
|
case 0x3c:
|
|
if (value8 != oldval) {
|
|
BX_INFO(("new irq line = %d", value8));
|
|
}
|
|
goto set_value;
|
|
break;
|
|
case 0x40:
|
|
value8 = (value8 & 0xc0) | 0x01;
|
|
case 0x41:
|
|
case 0x42:
|
|
case 0x43:
|
|
pm_base_change |= (value8 != oldval);
|
|
goto set_value;
|
|
break;
|
|
case 0x90:
|
|
value8 = (value8 & 0xf0) | 0x01;
|
|
case 0x91:
|
|
case 0x92:
|
|
case 0x93:
|
|
sm_base_change |= (value8 != oldval);
|
|
default:
|
|
set_value:
|
|
BX_ACPI_THIS s.pci_conf[address+i] = value8;
|
|
sprintf(szTmp2, "%02x", value8);
|
|
}
|
|
strrev(szTmp2);
|
|
strcat(szTmp, szTmp2);
|
|
}
|
|
if (pm_base_change) {
|
|
if (DEV_pci_set_base_io(BX_ACPI_THIS_PTR, read_handler, write_handler,
|
|
&BX_ACPI_THIS s.pm_base,
|
|
&BX_ACPI_THIS s.pci_conf[0x40],
|
|
64, &acpi_pm_iomask[0], "ACPI PM base"))
|
|
{
|
|
BX_INFO(("new PM base address: 0x%04x", BX_ACPI_THIS s.pm_base));
|
|
}
|
|
}
|
|
if (sm_base_change) {
|
|
if (DEV_pci_set_base_io(BX_ACPI_THIS_PTR, read_handler, write_handler,
|
|
&BX_ACPI_THIS s.sm_base,
|
|
&BX_ACPI_THIS s.pci_conf[0x90],
|
|
16, &acpi_sm_iomask[0], "ACPI SM base"))
|
|
{
|
|
BX_INFO(("new SM base address: 0x%04x", BX_ACPI_THIS s.sm_base));
|
|
}
|
|
}
|
|
strrev(szTmp);
|
|
BX_DEBUG(("ACPI controller write register 0x%02x value 0x%s", address, szTmp));
|
|
}
|
|
|
|
#endif // BX_SUPPORT_PCI
|