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cpudb
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fixed compilation w/o AVX
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2011-10-09 13:56:39 +00:00 |
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3dnow.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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access32.cc
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fixed dbg print mentioned in SF bug 3029271
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2011-09-22 22:08:18 +00:00 |
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access64.cc
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fixed dbg print mentioned in SF bug 3029271
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2011-09-22 22:08:18 +00:00 |
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access.cc
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implemented AVX instructions support
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2011-03-19 20:09:34 +00:00 |
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aes.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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apic.cc
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change BX_PANIC to BX_ERROR
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2011-09-18 17:36:54 +00:00 |
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apic.h
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Implemented VMX preemption timer VMEXIT control (patch by Jianan Hao)
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2011-07-03 15:59:48 +00:00 |
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arith8.cc
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Merge lazy flags optimization by Darek Mihocka.
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2011-09-12 19:36:53 +00:00 |
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arith16.cc
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Merge lazy flags optimization by Darek Mihocka.
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2011-09-12 19:36:53 +00:00 |
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arith32.cc
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Merge lazy flags optimization by Darek Mihocka.
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2011-09-12 19:36:53 +00:00 |
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arith64.cc
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Merge lazy flags optimization by Darek Mihocka.
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2011-09-12 19:36:53 +00:00 |
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avx2.cc
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- Added support for AVX and AVX2 instructions emulation, to enable configure
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2011-08-27 13:47:16 +00:00 |
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avx_fma.cc
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added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions
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2011-10-07 14:09:35 +00:00 |
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avx_pfp.cc
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MXCSR.FUZ is ignoired for F16 instructions
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2011-10-03 15:08:22 +00:00 |
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avx.cc
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avx2 added broadcast from register
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2011-08-29 21:00:25 +00:00 |
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bcd.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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bit16.cc
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lzcnt/tzcnt bmi instructions implemented
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2011-08-31 20:43:47 +00:00 |
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bit32.cc
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lzcnt/tzcnt bmi instructions implemented
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2011-08-31 20:43:47 +00:00 |
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bit64.cc
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lzcnt/tzcnt bmi instructions implemented
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2011-08-31 20:43:47 +00:00 |
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bit.cc
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MOVBE instruction exists only in memory form
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2011-08-25 21:20:50 +00:00 |
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bmi32.cc
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- Added support for AVX and AVX2 instructions emulation, to enable configure
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2011-08-27 13:47:16 +00:00 |
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bmi64.cc
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- Added support for AVX and AVX2 instructions emulation, to enable configure
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2011-08-27 13:47:16 +00:00 |
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call_far.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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cpu.cc
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- New way of CPUs scheduling in SMP mode brings up to 50% speedup to the
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2011-09-22 19:38:52 +00:00 |
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cpu.h
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added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions
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2011-10-07 14:09:35 +00:00 |
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cpuid.h
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disasm for FMA4, better dbg print SSE rounding control with MXCSR
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2011-10-06 20:33:10 +00:00 |
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crc32.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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crregs.cc
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more polishing for vmx configurability
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2011-09-26 18:08:31 +00:00 |
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crregs.h
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fixed compilation with x86-64=0
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2011-09-16 20:12:36 +00:00 |
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ctrl_xfer16.cc
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- 10% emulation speedup with handlers chaining optimization implemented. The
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2011-08-21 14:31:08 +00:00 |
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ctrl_xfer32.cc
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- 10% emulation speedup with handlers chaining optimization implemented. The
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2011-08-21 14:31:08 +00:00 |
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ctrl_xfer64.cc
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- 10% emulation speedup with handlers chaining optimization implemented. The
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2011-08-21 14:31:08 +00:00 |
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ctrl_xfer_pro.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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data_xfer8.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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data_xfer16.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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data_xfer32.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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data_xfer64.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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debugstuff.cc
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- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
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2011-09-25 17:36:20 +00:00 |
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descriptor.h
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- deleted executable properties from source files
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2011-04-03 10:29:19 +00:00 |
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exception.cc
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accessors for DR6 and DR7 fields
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2011-03-15 20:20:15 +00:00 |
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fetchdecode64.cc
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store modrm() for x87 in Ib() byte because x87 have no Ib()
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2011-09-20 06:02:27 +00:00 |
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fetchdecode_avx.h
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added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions
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2011-10-07 14:09:35 +00:00 |
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fetchdecode_sse.h
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- Added support for AMD SSE4A emulation, the instructions can be enabled
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2011-09-18 16:18:22 +00:00 |
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fetchdecode_x87.h
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- deleted executable properties from source files
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2011-04-03 10:29:19 +00:00 |
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fetchdecode.cc
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Move DAZ handling into softfloat library (for float16, float32 and float64 only) and cleanup SSE and AVX code
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2011-10-01 15:40:36 +00:00 |
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fetchdecode.h
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make RDTSC 'end of trace' instruction - guarantee that any pair ot RDTSC/RDTSCP on same CPU do not belong to same trace (and therefore will always update time and etc) - required for Win7 Thin
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2011-09-06 14:13:39 +00:00 |
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flag_ctrl_pro.cc
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Merge lazy flags optimization by Darek Mihocka.
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2011-09-12 19:36:53 +00:00 |
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flag_ctrl.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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fpu_emu.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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gather.cc
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rename avx2_gather.cc -> gather.cc
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2011-09-16 20:59:57 +00:00 |
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generic_cpuid.cc
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added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions
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2011-10-07 14:09:35 +00:00 |
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generic_cpuid.h
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Supply real VMX capabilities together with the CPU MODEL .bochsrc option.
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2011-09-26 12:31:40 +00:00 |
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i387.h
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Adding Id and Rev property to all files
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2011-02-24 21:54:04 +00:00 |
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ia_opcodes.h
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added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions
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2011-10-07 14:09:35 +00:00 |
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icache.cc
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Don't allow traces longer than cpu_loop can execute
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2011-09-21 20:28:29 +00:00 |
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icache.h
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set max trace length back to 32
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2011-08-21 16:44:02 +00:00 |
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init.cc
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Supply real VMX capabilities together with the CPU MODEL .bochsrc option.
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2011-09-26 12:31:40 +00:00 |
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instr.h
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store modrm() for x87 in Ib() byte because x87 have no Ib()
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2011-09-20 06:02:27 +00:00 |
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io.cc
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- 10% emulation speedup with handlers chaining optimization implemented. The
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2011-08-21 14:31:08 +00:00 |
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iret.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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jmp_far.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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lazy_flags.h
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Merge lazy flags optimization by Darek Mihocka.
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2011-09-12 19:36:53 +00:00 |
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load.cc
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- Added support for AVX and AVX2 instructions emulation, to enable configure
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2011-08-27 13:47:16 +00:00 |
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logical8.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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logical16.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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logical32.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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logical64.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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Makefile.in
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Move DAZ handling into softfloat library (for float16, float32 and float64 only) and cleanup SSE and AVX code
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2011-10-01 15:40:36 +00:00 |
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mmx.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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msr.cc
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#GP on reading VMX_EPT_VPID_CAP MSR when EPT and VPID disabled
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2011-09-26 20:36:26 +00:00 |
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mult8.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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mult16.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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mult32.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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mult64.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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paging.cc
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compilation w/o x86-64
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2011-09-26 19:48:58 +00:00 |
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proc_ctrl.cc
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enable Penryn VMX capabilities with VMX=1, VMX=2 is required for EPT and heavier stuff
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2011-09-26 19:36:20 +00:00 |
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protect_ctrl.cc
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small optimization
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2011-08-23 21:25:34 +00:00 |
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resolver.cc
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Adding Id and Rev property to all files
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2011-02-24 21:54:04 +00:00 |
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ret_far.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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segment_ctrl_pro.cc
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Adding Id and Rev property to all files
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2011-02-24 21:54:04 +00:00 |
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segment_ctrl.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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shift8.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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shift16.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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shift32.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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shift64.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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simd_int.h
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fixed for gather VSIB calculation
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2011-08-28 20:14:53 +00:00 |
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simd_pfp.h
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added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions
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2011-10-07 14:09:35 +00:00 |
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smm.cc
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syscall/sysret are not supported outside long64 mode in Intel CPUs
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2011-08-30 21:32:40 +00:00 |
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smm.h
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support for NX outside of x86-64.
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2011-08-10 22:04:33 +00:00 |
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soft_int.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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sse_move.cc
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- Added support for AVX and AVX2 instructions emulation, to enable configure
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2011-08-27 13:47:16 +00:00 |
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sse_pfp.cc
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Move DAZ handling into softfloat library (for float16, float32 and float64 only) and cleanup SSE and AVX code
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2011-10-01 15:40:36 +00:00 |
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sse_rcp.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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sse_string.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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sse.cc
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- Added support for AMD SSE4A emulation, the instructions can be enabled
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2011-09-18 16:18:22 +00:00 |
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stack16.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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stack32.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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stack64.cc
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reword all the CPU code in preparation for future CPU speedup implementation.
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2011-07-06 20:01:18 +00:00 |
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stack.h
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- deleted executable properties from source files
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2011-04-03 10:29:19 +00:00 |
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string.cc
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- 10% emulation speedup with handlers chaining optimization implemented. The
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2011-08-21 14:31:08 +00:00 |
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tasking.cc
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small favor to VMX OFF for code that compiled with VMX ON
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2011-08-09 20:50:51 +00:00 |
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todo
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added AVX FMA extensions support. The implementation is based on QEMU patch by Peter Maydell (fixed)
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2011-09-29 22:20:56 +00:00 |
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vm8086.cc
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Adding Id and Rev property to all files
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2011-02-24 21:54:04 +00:00 |
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vmcs.cc
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fixed warnings from compilation with mingw-gcc 4.6.1
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2011-09-30 20:38:18 +00:00 |
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vmexit.cc
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compilation w/o x86-64
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2011-09-26 19:48:58 +00:00 |
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vmx.cc
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compilation w/o x86-64
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2011-09-26 19:48:58 +00:00 |
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vmx.h
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added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
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2011-10-07 19:32:44 +00:00 |
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xmm.h
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- Added support for AVX and AVX2 instructions emulation, to enable configure
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2011-08-27 13:47:16 +00:00 |
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xsave.cc
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fixing xsave/xrstor flows with AVX
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2011-10-09 09:19:49 +00:00 |
