From zwane@linux.realnet.co.sz Thu Mar 28 11:59:40 2002 Date: Thu, 21 Mar 2002 08:21:29 +0200 (SAST) From: Zwane Mwaikambo To: Bochs Devel Subject: [Bochs-developers] [PATCH] bochs_smp_pge_pic_poll This patch is to get us a bit closer in booting linux 2.4 SMP (tested with 4-way) with all the bells and whistles. This was tested with 2.5.7-pre1, the PGE part of it we just play along and try follow the global page semantics (avoid flushing global pages in specific places) and is required for PPro+ kernels in linux. The PIC poll code allows polling mode, in this mode we don't have to do anything and let the host OS do everything. Zwane diff -ur bochs-1.3-zm1/cpu/cpu.h /build/source/bochs-1.3/cpu/cpu.h --- bochs-1.3-zm1/cpu/cpu.h Wed Mar 20 06:59:07 2002 +++ /build/source/bochs-1.3/cpu/cpu.h Wed Mar 20 22:26:31 2002 @@ -871,6 +871,7 @@ struct { bx_TLB_entry entry[BX_TLB_SIZE]; } TLB; + Boolean skip_global_pages; #endif struct { diff -ur bochs-1.3-zm1/cpu/paging.cc /build/source/bochs-1.3/cpu/paging.cc --- bochs-1.3-zm1/cpu/paging.cc Wed Oct 3 15:10:37 2001 +++ /build/source/bochs-1.3/cpu/paging.cc Wed Mar 20 23:09:51 2002 @@ -358,6 +358,7 @@ #if BX_USE_TLB unsigned i; unsigned wp, us_combined, rw_combined, us_current, rw_current; + skip_global_pages = false; for (i=0; iread_physical(this, + BX_CPU_THIS_PTR TLB.entry[i].pte_addr, + 4, &pte); + /* check if the global bit is set for this pte */ + if (pte & (1<<8)) + continue; } + + BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY; + } #endif // #if BX_USE_TLB invalidate_prefetch_q(); diff -ur bochs-1.3-zm1/cpu/proc_ctrl.cc /build/source/bochs-1.3/cpu/proc_ctrl.cc --- bochs-1.3-zm1/cpu/proc_ctrl.cc Mon Mar 11 08:07:35 2002 +++ /build/source/bochs-1.3/cpu/proc_ctrl.cc Wed Mar 20 22:42:19 2002 @@ -504,17 +504,14 @@ #else // Protected mode: #GP(0) if attempt to write a 1 to // any reserved bit of CR4 + if ((val_32 >> 10) & 0x7ff) + exception(BX_GP_EXCEPTION, 0, 0); - BX_INFO(("MOV_CdRd: ignoring write to CR4 of 0x%08x", - val_32)); - if (val_32) { - BX_INFO(("MOV_CdRd: (CR4) write of 0x%08x not supported!", - val_32)); - } - // Only allow writes of 0 to CR4 for now. - // Writes to bits in CR4 should not be 1s as CPUID - // returns not-supported for all of these features. - BX_CPU_THIS_PTR cr4 = 0; + BX_CPU_THIS_PTR cr4 = val_32; + // this also has the side effect of flushing the tlb + // including pages marked as global. + TLB_flush(); + skip_global_pages = (val_32 & (1<<4)) ? true: false; #endif break; default: @@ -1032,6 +1029,7 @@ model = 1; // Pentium Pro stepping = 3; // ??? features |= (1<<4); // implement TSC + features |= (1<<13); // support PGE # if BX_SUPPORT_APIC features |= (1<<9); // APIC on chip # endif diff -ur bochs-1.3-zm1/iodev/pic.cc /build/source/bochs-1.3/iodev/pic.cc --- bochs-1.3-zm1/iodev/pic.cc Tue Nov 27 20:15:39 2001 +++ /build/source/bochs-1.3/iodev/pic.cc Thu Mar 21 07:11:02 2002 @@ -243,7 +243,10 @@ poll = (value & 0x04) >> 2; read_op = (value & 0x03); if (poll) - BX_PANIC(("pic:master:OCW3: poll bit set")); + /* if we're in polling mode, the os executive has to do all the work, + * linux 2.4 does this for the timer interrupt on systems with an IOAPIC + */ + return; if (read_op == 0x02) /* read IRR */ BX_PIC_THIS s.master_pic.read_reg_select = 0; else if (read_op == 0x03) /* read ISR */ _______________________________________________ bochs-developers mailing list bochs-developers@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/bochs-developers