----------------------------------------------------------------------
Patch name: patch.tsc-zwane
Author: Zwane Mwaikambo <zwane@linuxpower.ca>
Date: Tue, 24 Sep 2002 19:44:51 -0400 (EDT)

Detailed description:

This patch will seperate the TSC from the other timers, this helps a lot 
in speeding up SMP boot and allows TSC synch to be possible. Seperation is 
definitely necessary for writing to the TSC (e.g. via WRMSR)

Minor bug fixes by Bryce:
1. I had to move the definition of tsc into BX_CPU_C.
2. remove duplicate case label BX_MSR_TSC in proc_ctrl.cc

Patch was created with:
  cvs diff -u
Apply patch to what version:
  cvs checked out on DATE, release version VER
Instructions:
  To patch, go to main bochs directory.
  Type "patch -p0 < THIS_PATCH_FILE".
----------------------------------------------------------------------

Index: pc_system.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/pc_system.cc,v
retrieving revision 1.23
diff -u -r1.23 pc_system.cc
--- pc_system.cc	20 Sep 2002 15:35:44 -0000	1.23
+++ pc_system.cc	28 Sep 2002 04:01:05 -0000
@@ -370,6 +370,12 @@
       UNUSED(this_ptr);
 
       bx_pc_system.counter++;
+
+#if BX_CPU_LEVEL >= 5
+      // This really belongs in CPU code...
+      for (int i = 0; i < BX_SMP_PROCESSORS; i++)
+	BX_CPU(i)->tsc++;
+#endif
 }
 
 #if BX_DEBUGGER
Index: cpu/cpu.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
retrieving revision 1.84
diff -u -r1.84 cpu.h
--- cpu/cpu.h	27 Sep 2002 09:56:40 -0000	1.84
+++ cpu/cpu.h	28 Sep 2002 04:01:09 -0000
@@ -1390,6 +1390,7 @@
 
 #if BX_CPU_LEVEL >= 5
   bx_regs_msr_t	msr;  
+  Bit64u tsc;
 #endif
 
   i387_t the_i387;
Index: cpu/init.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/init.cc,v
retrieving revision 1.32
diff -u -r1.32 init.cc
--- cpu/init.cc	22 Sep 2002 18:22:24 -0000	1.32
+++ cpu/init.cc	28 Sep 2002 04:01:10 -0000
@@ -497,7 +497,9 @@
 #if BX_CPU_LEVEL >= 4
   BX_CPU_THIS_PTR clear_AC ();
 #endif
-
+#if BX_CPU_LEVEL >= 5
+  BX_CPU_THIS_PTR tsc = 0;
+#endif
   BX_CPU_THIS_PTR inhibit_mask = 0;
   BX_CPU_THIS_PTR debug_trap = 0;
 
Index: cpu/proc_ctrl.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/proc_ctrl.cc,v
retrieving revision 1.51
diff -u -r1.51 proc_ctrl.cc
--- cpu/proc_ctrl.cc	25 Sep 2002 14:09:08 -0000	1.51
+++ cpu/proc_ctrl.cc	28 Sep 2002 04:01:13 -0000
@@ -1652,9 +1652,11 @@
   Boolean cpl = CPL;
   if ((tsd==0) || (tsd==1 && cpl==0)) {
     // return ticks
-    Bit64u ticks = bx_pc_system.time_ticks ();
-    RAX = (Bit32u) (ticks & 0xffffffff);
-    RDX = (Bit32u) ((ticks >> 32) & 0xffffffff);
+    Bit64u ticks = BX_CPU_THIS_PTR tsc;
+    EAX = (Bit32u) (ticks & 0xffffffff);
+    EDX = (Bit32u) ((ticks >> 32) & 0xffffffff);
+    EDX = (Bit32u) (ticks >> 32);
+
     //BX_INFO(("RDTSC: returning EDX:EAX = %08x:%08x", EDX, EAX));
   } else {
     // not allowed to use RDTSC!
@@ -1812,7 +1814,6 @@
 		/* The following registers are defined for Pentium only */
 		case BX_MSR_P5_MC_ADDR:
 		case BX_MSR_MC_TYPE:
-		case BX_MSR_TSC:
 		case BX_MSR_CESR:
 			/* TODO */
 			return;
@@ -1820,7 +1821,6 @@
 		/* These are noops on i686... */
 		case BX_MSR_P5_MC_ADDR:
 		case BX_MSR_MC_TYPE:
-		case BX_MSR_TSC:
 			/* do nothing */
 			return;
 
@@ -1830,6 +1830,12 @@
 		case BX_MSR_CTR1:
 			goto do_exception;
 #endif	/* BX_CPU_LEVEL == 5 */
+
+		case BX_MSR_TSC:
+		/* we ignore the high 32bits */
+		  BX_CPU_THIS_PTR tsc = (Bit64u)EAX;
+		  BX_INFO(("WRMSR: wrote %08x:%08x to MSR_TSC\n", 0, EAX));
+		  return;
 
 		/* MSR_APICBASE
 		   0:7		Reserved