From zwane@linux.realnet.co.sz Thu Mar 28 12:01:06 2002
Date: Thu, 28 Mar 2002 08:46:53 +0200 (SAST)
From: Zwane Mwaikambo <zwane@linux.realnet.co.sz>
To: Bryce Denney <bryce@tlw.com>
Cc: William Lee Irwin III <wli@holomorphy.com>
Subject: [BOCHS-SMP] processor priority

Hi Bryce,
	Did you written your processor priority patch? Here's something 
which is supposed to work if you haven't written one yet.

Cheers,
	Zwane

diff -ur /tmp/bochs-1.3-smp/cpu/apic.cc bochs-1.3-smp/cpu/apic.cc
--- /tmp/bochs-1.3-smp/cpu/apic.cc	Mon Mar 25 10:02:49 2002
+++ bochs-1.3-smp/cpu/apic.cc	Thu Mar 28 07:20:25 2002
@@ -703,10 +703,18 @@
 
 Bit8u bx_local_apic_c::get_ppr ()
 {
+  Bit32u tpr = (task_priority >> 4) & 0xf;		/* we want 7:4 */
+  Bit32u isrv = (highest_priority_int(isr) >> 4) & 0xf;	/* ditto */
+
+  if (tpr >= isrv)
+	proc_priority = task_priority & 0xff;
+  else
+	proc_priority = isrv << 4;		/* low 4 bits of PPR have to be cleared */
+	
   if (bx_dbg.apic)
-		BX_INFO(("WARNING: Local APIC Processor Priority not implemented, returning 0"));
-  // should look at TPR, vector of highest priority isr, etc.
-  return 0;
+		BX_INFO(("%s: get_ppr returning %#x", cpu->name, proc_priority));
+
+  return proc_priority & 0xff;
 }
 
 
diff -ur /tmp/bochs-1.3-smp/cpu/cpu.h bochs-1.3-smp/cpu/cpu.h
--- /tmp/bochs-1.3-smp/cpu/cpu.h	Thu Mar 28 06:16:24 2002
+++ bochs-1.3-smp/cpu/cpu.h	Thu Mar 28 06:40:53 2002
@@ -614,7 +614,7 @@
   // ISR=in-service register.  When an IRR bit is cleared, the corresponding
   // bit in ISR is set.  The ISR bit is cleared when 
   Bit8u isr[BX_LOCAL_APIC_MAX_INTS];
-  Bit32u arb_id, arb_priority, task_priority, log_dest, dest_format, spurious_vec;
+  Bit32u arb_id, arb_priority, task_priority, proc_priority, log_dest, dest_format, spurious_vec;
   Bit32u lvt[6];
 #define APIC_LVT_TIMER   0
 #define APIC_LVT_THERMAL 1

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