Stanislav Shwartsman
f5d55f5eb6
- Implemented Task Switch intercept in SVM, cleanup in task switch handling code
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- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
76ee7b499b
svm updates
2012-01-08 14:09:51 +00:00
Stanislav Shwartsman
269d5e3443
more SVM fixes
2012-01-01 20:26:23 +00:00
Stanislav Shwartsman
93523a657d
remove patch that always kept IF set after HLT - not needed anymore
2011-12-30 08:50:01 +00:00
Stanislav Shwartsman
abda3a967c
added two AMD CPUs to CPUDB
2011-12-29 14:23:22 +00:00
Stanislav Shwartsman
7f5f917a34
more SVM implementation
2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
c32eaa5d05
added more svm intercepts
2011-12-26 20:51:57 +00:00
Stanislav Shwartsman
8b4a2c2034
implemented some more intercepts.
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fixed compilation without SVM
2011-12-26 16:33:13 +00:00
Stanislav Shwartsman
a44c1b8e1e
SVM and VMX share tsc offset code
2011-12-25 19:53:23 +00:00
Stanislav Shwartsman
75bda1d5cd
implemented SVM emulation support for Bochs (incomplete yet)
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I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.
Also looking for anybody with existing SVM kernels - as simple as possible - for testing.
Status:
- exceptions intercept is not implemented yet
- IO intercept is not implemented yet
- MSR intercept is not implemented yet
- virtual interrupts are not implemented yet
- CPUID is not implemented yet
No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
cbbd8bfd46
fixed some warnings after compilation with msvcpp 2010
2011-12-10 18:58:25 +00:00
Stanislav Shwartsman
12ad45395b
enable Penryn VMX capabilities with VMX=1, VMX=2 is required for EPT and heavier stuff
2011-09-26 19:36:20 +00:00
Stanislav Shwartsman
62d0c8abf7
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
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32-bit CPU using Bochs binary compiled with x86-64 support.
The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
96cedbc756
continue handlers-chaining optimization: update time once per trace and not for every instruction
2011-09-06 15:35:39 +00:00
Stanislav Shwartsman
dfd769a102
- Fixed compilation issue with cpu-level=5
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- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b
syscall/sysret are not supported outside long64 mode in Intel CPUs
2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
fa930961c2
small optimization
2011-08-23 21:25:34 +00:00
Stanislav Shwartsman
0171324877
small favor to VMX OFF for code that compiled with VMX ON
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avoid function call when not in vmx guest.
2011-08-09 20:50:51 +00:00
Stanislav Shwartsman
17a94fc58e
warning fixes
2011-08-09 18:00:19 +00:00
Stanislav Shwartsman
78327d3e5e
First step toward completely configurable CPU.
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Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
f8e4e7f16b
clean up/fixed instrumentation examples + removed old 2-years old configure options check (deprecated)
2011-07-23 19:58:38 +00:00
Stanislav Shwartsman
cac3c836fa
fixed typo
2011-07-18 21:47:14 +00:00
Stanislav Shwartsman
cddd1e3758
MONITOR/MWAIT: Do monitor on cache line granularity only + bugfix with possible TLB caching of monitored line
2011-07-18 21:44:22 +00:00
Stanislav Shwartsman
f81e47cca2
it is better to handle A20 in paging already
2011-07-18 20:22:59 +00:00
Stanislav Shwartsman
28a58f4ea5
fix rdtscp code
2011-07-09 22:28:08 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
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Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
ee3f9e36cb
Implemented Supervisor Mode Execution Protection (SMEP)
2011-05-29 16:28:26 +00:00
Stanislav Shwartsman
024a1ace38
move X2APIC to be .bochsrc option, rework of the cpuid code
2011-04-21 13:27:42 +00:00
Stanislav Shwartsman
31dd6a70db
small cleanups
2011-03-20 21:16:45 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
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many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
a31103e7d8
optimize fetchdecode tables - part2
2011-01-21 16:07:51 +00:00
Stanislav Shwartsman
1bd512e98d
split more SSE ops, optimizations in MMX code
2010-12-25 17:04:36 +00:00
Stanislav Shwartsman
43600f3756
complete rework of SSE code
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next step - split all SSE opcodes by ModC0
2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
4a85a8680e
SSE optimization
2010-12-19 07:06:40 +00:00
Stanislav Shwartsman
8308a47168
trying to get rid of b1() in instruction class
2010-09-24 21:15:16 +00:00
Stanislav Shwartsman
1107ce138e
small fetchdecode optimization
2010-09-07 19:54:50 +00:00
Stanislav Shwartsman
55cb12badf
fixed missed canonical failure on system access
2010-07-22 20:12:25 +00:00
Stanislav Shwartsman
91ac0df65c
implemented GS/FS BASE access instructions published in _319433-007.pdf document
2010-07-22 16:41:59 +00:00
Stanislav Shwartsman
59ad9d8de8
Fixes
2010-07-15 20:18:03 +00:00
Stanislav Shwartsman
30fecf9792
changes in comments only
2010-04-22 17:51:37 +00:00
Stanislav Shwartsman
50462dde9a
RDTSCP could be run outside long64
2010-04-08 16:38:41 +00:00
Stanislav Shwartsman
9cece96d14
fixes
2010-04-04 18:46:03 +00:00
Stanislav Shwartsman
7c42447c77
move secondary VMEXEC controls to -enable-vmx=2 option
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EPT coming next
2010-04-03 07:30:23 +00:00
Stanislav Shwartsman
d39d485ece
changes variable name to better one
2010-04-03 05:59:07 +00:00
Stanislav Shwartsman
93220f6b6e
fixes
2010-04-02 21:22:17 +00:00
Stanislav Shwartsman
33262356ec
small optimization
2010-03-27 16:30:01 +00:00
Stanislav Shwartsman
f5ce2a7639
split crreg access functions to separate file
2010-03-25 21:33:07 +00:00
Stanislav Shwartsman
da656bf93d
optimization for paging disable mode + preparing for future
2010-03-19 17:00:05 +00:00
Stanislav Shwartsman
79466dffe2
apic virtualization + vmx fixes
2010-03-16 14:51:20 +00:00
