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49 Commits

Author SHA1 Message Date
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
dbb91069f4 Added SSE4_2 instructions emulation 2007-10-01 19:59:37 +00:00
Stanislav Shwartsman
3e3254ecc4 some speedup for SSE code - achived by code simplification 2007-09-20 22:55:03 +00:00
Stanislav Shwartsman
895891b673 Implemented #AC check under configure option 
Fixes in misaligned SSE support
 2007-07-31 20:25:52 +00:00
Stanislav Shwartsman
5189cfbf10 SSE4 support 2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
bdc4905c8a Correctly detect SSE2 and SSE instructions and #UD when SSE2 is OFF for SSE 2007-04-02 10:46:33 +00:00
Stanislav Shwartsman
26f08fdb2c Change my e-mail to #SF one 2007-03-23 21:27:13 +00:00
Stanislav Shwartsman
1ec33ec518 Correctly #UD on aliased instructions when no SSE2 is configured 2007-03-22 22:51:41 +00:00
Stanislav Shwartsman
f8003098b1 Rename SSE4 to SSE3E to match intel docs. SSE4 coming later ;) 
Fixed "last prefix" for REX in 64-bit mode
 2007-01-25 19:09:41 +00:00
Stanislav Shwartsman
16713b309d PALIGNR fixed 2006-05-16 16:20:26 +00:00
Stanislav Shwartsman
03eac64013 Added decoding of new SSE4 instructions (recently published in Intel docs) 
At least CPUID detects them correctly
The code is never tested (still) ! (but should work fine)
 2006-04-06 18:30:05 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash: 
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
 2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU 
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
 2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
0150904e9d Improve debug messages and optimize 2006-02-22 20:58:16 +00:00
Stanislav Shwartsman
5c58b22f44 Fixed opcode names according to Intel docs 
Fixed bug found during disasm validation
 2006-02-17 13:34:31 +00:00
Stanislav Shwartsman
90f899fd16 Fix bug in PMULUDQ SSE instruction 2006-01-18 18:39:17 +00:00
Stanislav Shwartsman
d1c722211e Fix duplicate opcodes, fix opcode names and disasm bugs 2005-09-23 16:45:41 +00:00
Stanislav Shwartsman
3d9ee328fb PMOVMSKB and PEXTRW instruction should zero-extend dest when in 64-bit mode 2005-09-12 18:08:35 +00:00
Stanislav Shwartsman
d10731f162 Update my e-mail in source files 
Update committed SF patches in changes
 2005-05-12 18:07:48 +00:00
Stanislav Shwartsman
3074078297 Added CVS version header to all the files. 
One more small change in APIC
 2005-03-19 20:44:01 +00:00
Stanislav Shwartsman
33b50ec4c4 For spammers o 2004-04-08 17:17:47 +00:00
Stanislav Shwartsman
cc7b85ae7e just update release dates 2004-02-13 21:27:45 +00:00
Stanislav Shwartsman
56beb4110c Little code optimization 2003-09-26 19:20:17 +00:00
Stanislav Shwartsman
b6ff1e6d9d dos2unix for softfloat 
fixed denormals handling for MUL/DIV instructions
 2003-05-26 19:30:33 +00:00
Stanislav Shwartsman
1d45167e5b Merged NEW-INSTRUCTIONS branch 2003-05-15 16:41:17 +00:00
Stanislav Shwartsman
ba2b84e604 Implemented MASKMOVQ and MASKMOVDQU instructions 2003-04-23 18:51:37 +00:00
Stanislav Shwartsman
8193a710ad Changed MMX/SSE/SSE2 diagnostic messages to be more informative 2003-03-21 20:33:23 +00:00
Stanislav Shwartsman
633d0b59fb clean up of error messages 2002-12-30 18:51:09 +00:00
Stanislav Shwartsman
7dcd9ab8ec * implemented MOVLHS/MOVHPS/MOVHLPS/MOVLHPS opcodes 
* another reorganization of SSE code
 2002-12-30 18:10:10 +00:00
Stanislav Shwartsman
7e41d08620 Fixed problem with shift imm instructions 2002-12-30 08:03:34 +00:00
Stanislav Shwartsman
e1d5cddc6d Fixed a problem with zero-count shift in following instructions: 
PSRAW_PqQq    (MMX)
PSRAD_PqQq    (MMX)
PSRAW_PqIb    (MMX)
PSRAD_PqIb    (MMX)

PSRAW_VdqWdq  (SSE)
PSRAD_VdqWdq  (SSE)
PSRAW_PdqIb   (SSE)
PSRAD_PdqIb   (SSE)

When register was shifted by 0 bits the result produced was incorrect.

Now Bochs fully passes MMX test provided by
Hentai Yagi [hentai_yagi@yahoo.com.au] !
 2002-12-29 21:14:25 +00:00
Stanislav Shwartsman
1cd38bb7dd Recommitted SSE code reorganization. 
Fix in FXSAVE/FXRESTOR opcodes -> If the OSFXSR bitCR4 is not set, the FXRSTOR instruction does not restore the states of the XMM and MXCSR registers.
 2002-12-22 20:13:00 +00:00
Bryce Denney
9b2914fd1d - Temporarily revert Stanislav's changes between 2002-12-18 and 2002-12-19. 
Because source files were added/removed it would require an update
  of the windows and macos project files, so I want to wait until after 2.0.
    M Makefile.in         1.51 back to 1.50
    M cpu.h               1.121 back to 1.120
    M fetchdecode.cc      1.37 back to 1.36
    M fetchdecode64.cc    1.33 back to 1.32
    M sse.cc              1.17 back to 1.16
    A sse2.cc             1.27 back to 1.26  (added back)
    R sse_move.cc         removed
    R sse_pfp.cc          removed
- to bring these changes back again, all we have to do is
  "cvs update -j tmp-before1 -j tmp-after1"
 2002-12-19 05:53:18 +00:00
Stanislav Shwartsman
aa361badf2 Reorganized SSE/SSE2 code 
sse.cc -> general SSE stuff and SSE integer (MMX extensions)
sse_move.cc -> memory transfer and shuffle opcodes
sse_pfp.cc -> packed floating point operations
 2002-12-18 22:33:44 +00:00
Stanislav Shwartsman
04c7d9301b implemented 
PINSRW_VdqEdIb
PEXTRW_VdqEdIb
PINSRW_PqEdIb
PEXTRW_PqEdIb

instructions
 2002-12-02 21:24:09 +00:00
Stanislav Shwartsman
bcd57bdcaf *** Current duplicate SSE/SSE2 instructions list *** 
MOVUPS_VpsWps  (0f 10) = MOVUPD_VpdWpd  (66 0f 10) = MOVDQU_VdqWdq (f3 0f 6f)
MOVUPS_WpsVps  (0f 11) = MOVUPD_WpdVpd  (66 0f 11) = MOVDQU_WdqVdq (f3 0f 7f)
MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28) = MOVDQA_VdqWdq (66 0f 6f)
MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29) = MOVDQA_WdqVdq (66 0f 7f)

MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

ANDPS_VpsWps   (0f 54) = ANDPD_VpdWpd   (66 0f 54) = PAND_VpdWpd   (66 0f db)
ANDNPS_VpsWps  (0f 55) = ANDNPD_VpdWpd  (66 0f 55) = PANDN_VpdWpd  (66 0f df)
ORPS_VpsWps    (0f 56) = ORPD_VpdWpd    (66 0f 56) = POR_VpdWpd    (66 0f eb)
XORPS_VpsWps   (0f 57) = XORPD_VpdWpd   (66 0f 57) = PXOR_VpdWpd   (66 0f ef)

Removed dupes
 2002-11-25 21:58:55 +00:00
Stanislav Shwartsman
9bf3b44665 Fixed a little logic problem with FPU TWD save/restore 2002-11-22 21:33:12 +00:00
Stanislav Shwartsman
2b2e773dde Fixed a problem in LDMXCSR instruction 
Beta version of FXSAVE/FXRSTOR instructions implementation
(still imcomplete, doesn't fully restore FPU state)
 2002-11-22 21:21:31 +00:00
Stanislav Shwartsman
3217759a75 Implemented 
PSHUFLW_VqWqIb, PSHUFHW_VqWqIb instructions
 2002-11-15 17:34:47 +00:00
Stanislav Shwartsman
88ce9917e6 Replace BX_PANIC to BX_INFO for FXSAVE/FXRSTOR instruction 
because their is required for booting Windows with SSE enabled.
 2002-11-15 13:10:06 +00:00
Stanislav Shwartsman
65b8712d04 More tuning of SSE 2002-11-14 19:59:29 +00:00
Stanislav Shwartsman
5803e20240 Changed policy of SSE/SSE2 checking 2002-11-13 21:00:05 +00:00
Stanislav Shwartsman
790430bf22 #UD exception condition for SSE instructions fixed 2002-11-08 20:27:42 +00:00
Stanislav Shwartsman
277f14dd76 Implemented PMOVMSKB_GdPRq instruction (SSE) 2002-10-19 21:46:07 +00:00
Stanislav Shwartsman
63ac78d496 Implemented MOVNTQ instruction 2002-10-19 21:28:50 +00:00
Stanislav Shwartsman
82c879717c add prepareSSE for SSE2 only. SSE2 only not allowed by configure script but for debug issues it may be useful to enable SSE2 only ... 2002-10-19 21:01:24 +00:00
Stanislav Shwartsman
6cd078b777 Add opcode name to the information message in case of MMX/SSE/SSE2 instruction is not supported 2002-10-19 20:58:18 +00:00
Stanislav Shwartsman
194952a53d Merged BOCHS-SSE branch 2002-10-16 17:37:35 +00:00
Stanislav Shwartsman
b4f1a57924 Merged BOCHS-SSE branch with latest main trunk sources 2002-10-11 17:56:56 +00:00