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43 Commits

Author SHA1 Message Date
Stanislav Shwartsman
4b03966176 Implemented VDBPSADBW AVX512BW instruction 
The only missing AVX512BW/AVX512DQ opcodes are now:

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-08-05 20:18:42 +00:00
Stanislav Shwartsman
94864fb9bc Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20. 
https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf

Most of the instructions are implemented, more on the way.

+ few bugfixes for legacy AVX-512 emulation

AVX-512: Fixed bug in VCMPPS masked instruction implementation with 512-bit data size
AVX-512: Fixed AVX-512 masked convert instructions with non-k0 mask (behaved as non masked versions)
AVX-512: Fixed missed #UD due to invalid EVEX prefix fields for several AVX-512 opcodes (VFIXUPIMMSS/SD, FMA)
 2014-07-18 11:14:25 +00:00
Stanislav Shwartsman
a21f03e69b implemented few more avx-512 cvt opcodes 2014-01-21 21:00:40 +00:00
Stanislav Shwartsman
15756a31cd implemented EVEX MOVD/MOVQ opcodes, fixes in softfloat 2013-12-13 12:05:47 +00:00
Stanislav Shwartsman
d20c81417c Implemented VSHUFF32x4/64x2, VSHUFI32x4/64x2 AVX512 instructions 
Implemented AVX512 blend instructions
Do not allow setting of EVEX.b in reg form when no floating point exceptions could be generated by instruction
 2013-12-09 19:09:37 +00:00
Stanislav Shwartsman
ca2793ac76 Debugger: fixed param tree access to 64-bit variables (need to use get64() instead of get()) 
Debugger: if AVX-512 if not supported by current configuration do not print high256 of vector registers and zmm15..zmm31 in AVX command
Implement VBROADCASTF64x4, VBROADCASTF32x4, VBROADCASTFI64x4, VBROADCASTI32x4 AVX-512 instructions
Fetchdecode optimizations and bugfixes
 2013-12-05 19:17:16 +00:00
Stanislav Shwartsman
cfc8a0ad38 get rid of BX_MEM_NO_VVV decoding form (by splitting just two opcode groups using Split11B) 2013-12-04 20:15:22 +00:00
Stanislav Shwartsman
582bf84bae apply same optimization to disasm as well 2013-10-10 21:00:26 +00:00
Stanislav Shwartsman
46e36b463b size-optimization for SSE opcode tables 2013-10-10 20:21:15 +00:00
Stanislav Shwartsman
09254eb474 avx512 implementation fixes and next steps 2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
059769e2a6 disasm bug fixes 2013-10-06 20:42:13 +00:00
Stanislav Shwartsman
ff79cbd596 Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm) 
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.

Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
 2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
0cb0acc30f added evex decode tables - next step to populate them :) 2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
7297323c69 First step of AVX512 support implementation (simplest) 
decode and implement KMASK manipulation instructions
disasm: coming soon
 2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
a6b85d9443 compress xop tables for vex.l - smaller binary size 2013-09-06 18:56:46 +00:00
Stanislav Shwartsman
0fd4e3450c update (c) for few files 2013-09-05 18:40:14 +00:00
Stanislav Shwartsman
69f947cef2 fixes and small optimizations for avx and xop decoding 2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
897bf85494 fixed bug in fma4 decoding - found now thanks to new tables re-org 2013-09-04 18:37:49 +00:00
Stanislav Shwartsman
2f957bf142 re-arrange AVX/XOP table to avoid redundant multiplication in decode. TODO: compress the tables 2x using aliases 2013-09-04 18:36:01 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
3a7e336cb6 more opcode alias - now VEX.W alias 2013-08-21 18:45:36 +00:00
Stanislav Shwartsman
115ec37a4c make decoder tables smaller using decode aliases 2013-08-21 04:52:49 +00:00
Stanislav Shwartsman
db4d75317a fixed small avx issues 2012-12-11 21:01:05 +00:00
Stanislav Shwartsman
318ad5e26d optimize avx stores 2012-12-10 14:43:21 +00:00
Stanislav Shwartsman
182ad65ea3 changes in avx emulation code 2012-12-09 16:42:48 +00:00
Stanislav Shwartsman
cc694377b9 Standartization of Bochs instruction handlers. 
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
 2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
874ba7388d coding style change 2012-06-30 19:33:49 +00:00
Stanislav Shwartsman
39f3051ce5 fixed opcode primitive used for AVX instructions reading only half register (8byte) from the memory 2012-06-30 19:31:32 +00:00
Stanislav Shwartsman
b1a6b34616 implemented PERMIL2PS/PERMIL2PD XOP instructions 2011-10-20 17:37:57 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions. 
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
 2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
2580d8c46d added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions 2011-10-07 14:09:35 +00:00
Stanislav Shwartsman
6751af5d8e added AVX FMA extensions support. The implementation is based on QEMU patch by Peter Maydell (fixed) 2011-09-29 22:20:56 +00:00
Stanislav Shwartsman
8099fd9efd implemented alternative access to CR8: AMD feature. Lock CR0 -> CR8 2011-09-03 15:22:56 +00:00
Stanislav Shwartsman
1f5e036695 lzcnt/tzcnt bmi instructions implemented 2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
c30275016e avx2 added broadcast from register 2011-08-29 21:00:25 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
dd79431702 rename AVX handlers - match their real operands 2011-08-20 15:10:18 +00:00
Stanislav Shwartsman
2f582db722 compile less stuff for cpu-level=5 2011-06-26 19:15:30 +00:00
Stanislav Shwartsman
778154b3b2 one more fix 2011-06-11 18:27:37 +00:00
Stanislav Shwartsman
ef38c9e235 fix decode for VCVTPH2PS 2011-06-11 18:26:05 +00:00
Stanislav Shwartsman
8399dee24c implemented AVX float16 convert instructions 2011-06-11 13:12:32 +00:00
Stanislav Shwartsman
7664c55b08 first fixups after AVX 
(and for AVX)
 2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00