Stanislav Shwartsman
41f926628c
fixed bug in LOAD_BROADCAST_MASK_Half_VectorD method
2014-02-11 20:13:42 +00:00
Stanislav Shwartsman
b510cf794b
complete compressed displ feature support, bugfixes in AVX-512 code
2014-02-11 16:10:31 +00:00
Stanislav Shwartsman
ac06ee46ae
Implemented VPMOVSX*/VPMOVZX* AVX-512 instructions
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Now only missed AVX-512 opcodes now are:
512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH
512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD
512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
2014-02-02 19:56:08 +00:00
Stanislav Shwartsman
ccb1d86d6e
code cleanups
2013-12-09 20:36:24 +00:00
Stanislav Shwartsman
d20c81417c
Implemented VSHUFF32x4/64x2, VSHUFI32x4/64x2 AVX512 instructions
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Implemented AVX512 blend instructions
Do not allow setting of EVEX.b in reg form when no floating point exceptions could be generated by instruction
2013-12-09 19:09:37 +00:00
Stanislav Shwartsman
4c78ca8c1c
implemented mask load for most of the load+op instructions. all take care for instructions which do not support maksing of memory exceptions (shuffle and permutes)
2013-12-08 21:54:59 +00:00
Stanislav Shwartsman
a5153c348f
fixed bugs in vcmp* avx512 opcodes
2013-12-03 22:16:22 +00:00
Stanislav Shwartsman
6d9b16e0f7
Implemented VCMPPS/PD/SS/SD AVX512 instructions
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Implemented AVX512 shift/rotate instructions
2013-12-03 15:44:23 +00:00
Stanislav Shwartsman
ba505677d2
bugfix for avx-512 masked load with mask all-zero
2013-12-02 20:46:26 +00:00
Stanislav Shwartsman
79456eb7e1
Implemented VPCMP* AVX512 instructions
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Implemented VMOVNTPS/PD/DQ AVX512 instructions
Implemented VMOVNTDQA AVX512 instruction
Bugfixes for AVX-512
2013-12-02 18:05:18 +00:00
Stanislav Shwartsman
e1512ccaf8
fixed warning under new MSDEV compiler
2013-10-05 19:35:00 +00:00
Stanislav Shwartsman
8b3a0acde9
implement first EVEX instructions - VADDPS/PD/SS/SD
2013-09-19 18:31:30 +00:00
Stanislav Shwartsman
1cebe5f83d
rellback part of commit with xmm register access interface changes - doesn't work for big endian hosts
2013-09-16 19:10:42 +00:00
Stanislav Shwartsman
0cb0acc30f
added evex decode tables - next step to populate them :)
2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
a6b85d9443
compress xop tables for vex.l - smaller binary size
2013-09-06 18:56:46 +00:00
Stanislav Shwartsman
69f947cef2
fixes and small optimizations for avx and xop decoding
2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
748a0da712
one more step in the way towards avx-512 which have more vector registers
2013-08-24 12:12:10 +00:00
Stanislav Shwartsman
2dbe81db51
first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel
2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
ce2751a13c
move misaligned_sse from compile time to .bochsrc option
2012-12-20 19:43:11 +00:00
Stanislav Shwartsman
182ad65ea3
changes in avx emulation code
2012-12-09 16:42:48 +00:00
Stanislav Shwartsman
c41cbe6d56
Link traces over taken branch optimization which makes handlers chaining even more efficient.
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I observed 5% speedup in all disk images over 2.6pre1.
The change is safe (passed all regressions) and I will be glad to make it into Bochs 2.6!
2012-08-21 19:58:41 +00:00
Stanislav Shwartsman
9d802e2762
very small cleanup
2012-05-05 18:40:37 +00:00
Stanislav Shwartsman
cbbd8bfd46
fixed some warnings after compilation with msvcpp 2010
2011-12-10 18:58:25 +00:00
Stanislav Shwartsman
44241a1e56
- Added support for AVX and AVX2 instructions emulation, to enable configure
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with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
...
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
31be835056
bugfix + rename function
2011-06-14 19:56:28 +00:00
Volker Ruppert
c78026a9a2
- deleted executable properties from source files
2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
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many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
b5ebe5865e
Fixes for incoming bug report, missed changes in CVS, repository fixups and etc
2011-02-11 09:56:23 +00:00
Stanislav Shwartsman
2ce1bd299c
conditional compiling with misaligned sse
2011-01-12 20:16:25 +00:00
Stanislav Shwartsman
f705cbbc63
rename functions
2010-12-25 19:34:43 +00:00
Stanislav Shwartsman
d0ee1c1b80
Fixed for compilation with cpu-level=3
2010-12-25 15:00:20 +00:00
Stanislav Shwartsman
040a8e1a3a
split bunch of SSE opcodes
2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
709059ddcc
integrate misaligned SSE into code
2010-12-22 21:24:19 +00:00
Stanislav Shwartsman
43600f3756
complete rework of SSE code
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next step - split all SSE opcodes by ModC0
2010-12-22 21:16:02 +00:00
