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77 Commits

Author SHA1 Message Date
Stanislav Shwartsman
f5d55f5eb6 - Implemented Task Switch intercept in SVM, cleanup in task switch handling code 
- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
 2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
3c0d712146 SVM fixes 2011-12-31 13:58:55 +00:00
Stanislav Shwartsman
46d8a5894e removed bad RDMSR/WRMSR check which disabled access to AMD extended MSRs 2011-12-31 12:37:35 +00:00
Stanislav Shwartsman
0a14f08f16 completing SVM coding, missed - CPUID, extended APIC 2011-12-28 16:12:28 +00:00
Stanislav Shwartsman
7f5f917a34 more SVM implementation 2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
6ae86a059b firt cleanup in SVM code. added intercept check for MSR and IO 2011-12-26 19:57:39 +00:00
Stanislav Shwartsman
c74f590077 implemented TSC-Deadline APIC timer mode 2011-11-21 12:51:50 +00:00
Stanislav Shwartsman
9be8552b80 - Implemented VM Functions support and EPTP-Switching VM Functions 
- Added VMEXIT conditions for INVPCID instruction

Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
 2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
275194fb32 #GP on reading VMX_EPT_VPID_CAP MSR when EPT and VPID disabled 2011-09-26 20:36:26 +00:00
Stanislav Shwartsman
62d0c8abf7 - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 
32-bit CPU using Bochs binary compiled with x86-64 support.

The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
 2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
dfd769a102 - Fixed compilation issue with cpu-level=5 
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
 2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b syscall/sysret are not supported outside long64 mode in Intel CPUs 2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
fa930961c2 small optimization 2011-08-23 21:25:34 +00:00
Stanislav Shwartsman
002e7a3818 MSR_TSC_AUX is not available without RDTSCP 2011-08-21 19:09:35 +00:00
Stanislav Shwartsman
ed9b8478b5 undo RDTSC commit 2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf separate TSC to uniq feature that can be disabled in CPU configuration 2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
e50e187128 #GP on EFER access when not supported 2011-08-14 20:41:46 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
360481b391 infastructure for RDMSR/WRMSR control for cpuid class 
now the order is going to be:

1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
 2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
0171324877 small favor to VMX OFF for code that compiled with VMX ON 
avoid function call when not in vmx guest.
 2011-08-09 20:50:51 +00:00
Stanislav Shwartsman
e48765a511 VMX fixed, cleanups 2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
78327d3e5e First step toward completely configurable CPU. 
Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
 2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
024a1ace38 move X2APIC to be .bochsrc option, rework of the cpuid code 2011-04-21 13:27:42 +00:00
Volker Ruppert
c78026a9a2 - deleted executable properties from source files 2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
acd320699d small cleanups 2011-03-14 06:25:54 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
5ea2591cd9 fixes 2010-10-07 20:40:01 +00:00
Stanislav Shwartsman
32ff6e4879 MSR BX_DEBUG prints 2010-05-16 13:56:22 +00:00
Stanislav Shwartsman
6e1204cb84 Merged X2APIC + X2APIC virtualization 2010-04-08 15:50:39 +00:00
Stanislav Shwartsman
df7db31fb4 EPT + VPID - VMXx2 support 2010-04-07 17:12:17 +00:00
Stanislav Shwartsman
b4cd188f07 Update (c) 2010-04-04 19:56:55 +00:00
Stanislav Shwartsman
7c42447c77 move secondary VMEXEC controls to -enable-vmx=2 option 
EPT coming next
 2010-04-03 07:30:23 +00:00
Stanislav Shwartsman
d39d485ece changes variable name to better one 2010-04-03 05:59:07 +00:00
Stanislav Shwartsman
dc732f21bc MSR_PAT VMX support 2010-03-26 21:26:08 +00:00
Stanislav Shwartsman
15cba8d09a fail on obviosly not-supported MSRs 2010-03-19 21:04:00 +00:00
Stanislav Shwartsman
f0ac7c576e enable secondary proc-based ctrls 2010-03-15 15:48:01 +00:00
Stanislav Shwartsman
cffe32dd2c remove unused param from exception() call 2010-03-14 15:51:27 +00:00
Stanislav Shwartsman
97b4155f31 VMX_MSR_MISC implemented 2010-03-12 21:20:42 +00:00
Stanislav Shwartsman
380bf0f4d3 extra checkin to msr.cc 2010-03-12 11:30:04 +00:00
Stanislav Shwartsman
4ce211e358 MWAIT_IS_NOP option 2010-03-12 11:28:59 +00:00
Stanislav Shwartsman
7357d1664e fix 2010-03-06 17:09:25 +00:00
Stanislav Shwartsman
a217b7b08e fix 2010-03-06 17:07:25 +00:00
Stanislav Shwartsman
5d2c2879a7 IA32_FEATURE_CONTROL_MSR is implemented 2010-03-06 16:59:05 +00:00
Stanislav Shwartsman
189553d702 bugfix 2010-03-05 08:54:07 +00:00
Stanislav Shwartsman
14b578938d bugfixes and cleanups 2010-03-03 14:33:35 +00:00
Stanislav Shwartsman
927c3594d6 enable compilation with CPU_LEVEL <= 6 
converted SEP to runtime option as well
 2010-02-26 11:44:50 +00:00
Stanislav Shwartsman
71bb10f98c move ignore-bad-msrs to runtime option in ,bochsrc 2009-11-13 15:55:46 +00:00
Stanislav Shwartsman
98ae54675c more MTRR res bits 2009-11-04 17:04:28 +00:00
Stanislav Shwartsman
074d2e6a95 fixed merge problem from my prev commit 2009-11-04 06:46:04 +00:00