but in case you want a few %% of extra emulation performance - it is still possible to disable it with configure option.
most guests I saw do not use it !
for CPU emulation performance reasons, the alignment check compilation
still can be enabled using configure option --enable-alignment-check.
There is no software in the world which enable #AC exception checking, this
x86 feature is completely legacy but its emulation support costs up to 3-5%
emulation speed.
The checking for #AC exception enable still will be done, if
CPL == 3, EFLAGS.AC = 1 and CR0.AM = 1
but the alignment check is not compiled in, the Bochs will PANIC with corresponding message.
You can press 'always continue' and ignore the PANIC, the simulation will continue as if alignment checking is not enabled.
The problem with Parity is it is generally referenced very rarely so the current lazy flags code is not efficient to updated Parify flag only (because it updates low 8 bits of .result value the existing Zero Flag has to be shadowed in .auxbits.
So I flipped it around, to make Parity be shadowed in auxbits. .result now is only needed to derive Zero Flag, and both Sign and Parify are derived from .result + .auxbits (as Zero Flag is now). For the 90% of the conditional jumps that are JZ or JNZ, this is a speedup.
Parity is now derived from 8 bits in .result and 8 bits in .auxbits, and Sign is derived from one flag in .result and 1 bit in .auxbits by XOR-ing them all together. It makes the code sequences for SAHF and POPF simpler too.
Added phenom_8650_toliman <AMD Phenom X3 8650 (Toliman)> comment into .bochsrc example with all other supported CPU configs.
Added missed SVM definitions into Toliman CPUDB module
------------
Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.
! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.
Some CPUID modules rework done to enable Toliman configuration.
Ckean up 'executable' attribute from all CPU source files.
- VMX: EPT reserved bits set should cause EPT misconfiguration and not EPT violation
- VMX: EPT walk for guest CR3 address should be considered as 'page walk'