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54 Commits

Author SHA1 Message Date
Stanislav Shwartsman
9d8d895b52 cpuid fixes 2014-03-15 20:19:30 +00:00
Stanislav Shwartsman
2b83146ae2 more avx-512 instructions implemented 2013-12-01 19:39:18 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
fd71b03353 add some definitions introduced in recent Intel SDM extensions document (rev015) 2013-07-23 20:51:52 +00:00
Stanislav Shwartsman
c96f5e27a9 flush tlb also when cr4.smap changes 2013-01-14 17:02:51 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
ec06475dbf improve x86 hw breakpoint handling 2012-07-11 15:07:54 +00:00
Stanislav Shwartsman
6ae86a059b firt cleanup in SVM code. added intercept check for MSR and IO 2011-12-26 19:57:39 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
88a58b3781 fixed compilation with x86-64=0 2011-09-16 20:12:36 +00:00
Stanislav Shwartsman
dfd769a102 - Fixed compilation issue with cpu-level=5 
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
 2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b syscall/sysret are not supported outside long64 mode in Intel CPUs 2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
6606c62439 cr4 available since Pentium only 2011-08-16 16:49:04 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
2ee0029749 extract ffxsr support to separate CPU feature 2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
ee3f9e36cb Implemented Supervisor Mode Execution Protection (SMEP) 2011-05-29 16:28:26 +00:00
Stanislav Shwartsman
6ace540891 update for rev39 of Intel SDM 2011-05-28 20:20:25 +00:00
Volker Ruppert
c78026a9a2 - deleted executable properties from source files 2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
31dd6a70db small cleanups 2011-03-20 21:16:45 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
6deb746464 do not handle reserved bits yet 2011-03-15 20:22:17 +00:00
Stanislav Shwartsman
63fe52f601 accessors for DR6 and DR7 fields 2011-03-15 20:20:15 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
7f7c249934 disasm and some cpuid code according to recently published AVX_319433-007.pdf document 2010-07-22 15:12:08 +00:00
Stanislav Shwartsman
74b87d2b68 fixes for CPUID and alloweds bits in CRs 2010-05-12 21:33:04 +00:00
Stanislav Shwartsman
f95ddc4029 Debug Extensions was introduced in Pentium 2010-05-12 18:48:51 +00:00
Stanislav Shwartsman
ca95477b7f Implement x86-64 PCID extension 2010-04-29 19:34:32 +00:00
Stanislav Shwartsman
6d01eb5c1f announce (not implement yet) PCID 2010-03-31 14:00:46 +00:00
Stanislav Shwartsman
e7933d9dc2 enable EFER_MSR VMX controls 2010-03-27 09:27:40 +00:00
Stanislav Shwartsman
a220edc5bb compile fixes 2010-03-26 11:09:12 +00:00
Stanislav Shwartsman
f5ce2a7639 split crreg access functions to separate file 2010-03-25 21:33:07 +00:00
Stanislav Shwartsman
5b6a14656d Make XSAVE as runtime option 2010-02-26 22:53:43 +00:00
Stanislav Shwartsman
033a20b3b2 allow to configure CPU features at runtime - implemened on example of SSE/AES/MOVBE/POPCNT 2010-02-25 22:04:31 +00:00
Stanislav Shwartsman
6d71bdb785 cleanups and optimizations 2009-11-02 15:00:47 +00:00
Stanislav Shwartsman
7254ea36a1 copyright fixes + small optimization 2009-10-14 20:45:29 +00:00
Stanislav Shwartsman
8a95120e12 deprecate --enable-vme option, now it will be supported iff CPU_LEVEL >= 5 (like in real life) 2009-08-10 15:44:50 +00:00
Stanislav Shwartsman
f8185a6bc6 Added Intel VMX emulation to Bochs CPU 2009-01-31 10:43:24 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
6451356d2b make function to calculate allowed bits in cr4 2009-01-10 10:37:23 +00:00
Stanislav Shwartsman
87396f051a msr phy addr check use new function 2009-01-02 13:23:06 +00:00
Stanislav Shwartsman
e182e74a4d Added ability to define user MSRs spec for emulated CPU 2008-12-28 20:30:48 +00:00
Stanislav Shwartsman
f9ce1171fe rename crreg accessors 2008-12-06 10:21:55 +00:00
Stanislav Shwartsman
b3bbf8ded2 define generic MSR 2008-12-05 13:10:51 +00:00
Stanislav Shwartsman
892fa99c6f - prefetch hint should be NOP when use in register mode 
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
  even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
 2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
e91409704f Convert EFER to val32 register, similar to other control registers 2008-03-31 20:56:27 +00:00
Stanislav Shwartsman
b929a2b2b8 Fixed minor issues - compilation and not only 2008-02-13 17:06:44 +00:00
Stanislav Shwartsman
457152334e step2 in XSAVE implementation 2008-02-13 16:45:21 +00:00
Stanislav Shwartsman
8615022962 Added first stubs for XSAVE/XRESTOR implementation 
Disassemble XSAVE/XRSTOR instructions (4 instructions)
Update CHANGES - a bit speculatively
 2008-02-12 22:41:39 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00