5 Commits

Author	SHA1	Message	Date
Stanislav Shwartsman	e2f0880f1c	support more than 32-bit cpu features vector	2011-09-14 20:22:24 +00:00
Stanislav Shwartsman	1b27438146	cleanups + small code reorg	2011-08-10 20:31:29 +00:00
Stanislav Shwartsman	360481b391	infastructure for RDMSR/WRMSR control for cpuid class ... now the order is going to be: 1. MSRs emulated in Bochs (msr.cc) 2. MSRs emulated in model specific derivative class of cpuid_t 3. MSR can be loaded from msrs.def file 4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option	2011-08-09 22:11:56 +00:00
Stanislav Shwartsman	1068b4bd8c	cleanup	2011-08-03 21:46:46 +00:00
Stanislav Shwartsman	075db389a9	added atom n270 cpuid + small fixes	2011-08-03 17:49:49 +00:00