Commit Graph

420 Commits

Author SHA1 Message Date
instinc
01b699af16 as per bug report 498386, line 550 was causing a panic which has been disabled 2002-04-11 00:36:02 +00:00
Bryce Denney
49decc485c - when merging EDX and EAX to create the apic base address, add
a typecast to Bit64u before shifting left by 32.  Otherwise
  the EDX<<32 would overflow on 32 bit machines and the address would
  be wrong.
2002-04-03 15:12:22 +00:00
Bryce Denney
640d71d017 - check in Zwane Mwaikambo's MSR patch: patch.msr. 2002-03-27 16:04:05 +00:00
Bryce Denney
976e0b67d9 - clarify panic message. It panics if HLT is executed from segment 0xf000,
in other words from ROM BIOS code.
2001-11-18 16:32:40 +00:00
Bryce Denney
e0b4801b1f - commit Roland Mainz's idle hack as a configure option. To try it,
configure with --enable-idle-hack.  I have moved most of the code into
  x.cc since it is X windows specific.
2001-11-12 00:45:09 +00:00
Bryce Denney
b86dbe1f3c - committed patches/patch.no-busy-in-tr-cache. I'm leaving the patch
lying around for a while in case it needs to be reverted.
2001-10-09 21:15:14 +00:00
Bryce Denney
daf2a9fb55 - add RCS Id to header of every file. This makes it easier to know what's
going on when someone sends in a modified file.
2001-10-03 13:10:38 +00:00
Bryce Denney
4073d65f4d - apply patch [ #455014 ] CR0 bug in 80486, described as:
> In the register CR0, when the bit PM is enabled, the bit 4 is 0
  > when should be 1.
  Another fix from an anonymous donor.
2001-09-19 17:36:54 +00:00
Todd T.Fries
cd9733391b AtheOS triggers this, move to debug 2001-08-24 21:02:37 +00:00
Todd T.Fries
2bbb1ef8eb strip '\n' from BX_{INFO,DEBUG,ERROR,PANIC}
don't need it, moved the output of it into the general io functions.
saves space, as well as removes the confusing output if a '\n' is left off
2001-05-30 18:56:02 +00:00
Todd T.Fries
e291dd17d4 demote BX_INFO to BX_ERROR 2001-05-25 22:17:51 +00:00
Bryce Denney
49664f7503 - parts of the SMP merge apparantly broke the debugger and this revision
tries to fix it.  The shortcuts to register names such as AX and DL are
  #defines in cpu/cpu.h, and they are defined in terms of BX_CPU_THIS_PTR.
  When BX_USE_CPU_SMF=1, this works fine.  (This is what bochs used for
  a long time, and nobody used the SMF=0 mode at all.)  To make SMP bochs
  work, I had to get SMF=0 mode working for the CPU so that there could
  be an array of cpus.

  When SMF=0 for the CPU, BX_CPU_THIS_PTR is defined to be "this->" which
  only works within methods of BX_CPU_C.  Code outside of BX_CPU_C must
  reference BX_CPU(num) instead.
- to try to enforce the correct use of AL/AX/DL/etc. shortcuts, they are
  now only #defined when "NEED_CPU_REG_SHORTCUTS" is #defined.  This is
  only done in the cpu/*.cc code.
2001-05-24 18:46:34 +00:00
Bryce Denney
26cf93f455 - fixed stupid bug in my RDTSC code, which made the TSD bit
(time stamp disable) not work correctly
2001-05-24 18:03:14 +00:00
Bryce Denney
3503104390 - configure turns on APIC when cpu level > 5
- now the APIC feature bit is really controlled by cpu level and
  BX_APIC_SUPPORT, so it won't go on at the wrong time.
2001-05-23 15:54:05 +00:00
Bryce Denney
e61d00351f - merged BRANCH-smp-bochs into main branch. For details see comments
in BRANCH-smp-bochs revisions.
- The general task was to make multiple CPU's which communicate
  through their APICs.  So instead of BX_CPU and BX_MEM, we now have
  BX_CPU(x) and BX_MEM(y).  For an SMP simulation you have several
  processors in a shared memory space, so there might be processors
  BX_CPU(0..3) but only one memory space BX_MEM(0).  For cosimulation,
  you could have BX_CPU(0) with BX_MEM(0), then BX_CPU(1) with
  BX_MEM(1).  WARNING: Cosimulation is almost certainly broken by the
  SMP changes.
- to simulate multiple CPUs, you have to give each CPU time to execute
  in turn.  This is currently implemented using debugger guards.  The
  cpu loop steps one CPU for a few instructions, then steps the
  next CPU for a few instructions, etc.
- there is some limited support in the debugger for two CPUs, for
  example printing information from each CPU when single stepping.
2001-05-23 08:16:07 +00:00
Todd T.Fries
a628039f5f report undefined opcode if not implemented instead of panicing for RDTSC 2001-05-16 17:27:01 +00:00
Todd T.Fries
3c7414a418 error and undefined opcode + typo with BX_INFO in code only used on i386's 2001-05-16 16:50:04 +00:00
Todd T.Fries
bdb89cd364 merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.

In general this provides a generic interface for logging.

logfunctions:: is a class that is inherited by some classes, and also
.   allocated as a standalone global called 'genlog'.  All logging uses
.   one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
.   class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
.   respectively.
.
.   An example usage:
.     BX_INFO(("Hello, World!\n"));

iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance.  It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf().  At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.

More cleanup is coming, but this works for now.  If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.

Comments, bugs, flames, to me: todd@fries.net
2001-05-15 14:49:57 +00:00
Bryce Denney
a6fef54678 - update copyright dates to 2001 for all mandrake headers
- for bochs files with other header, replaced with current mandrake header
2001-04-10 02:20:02 +00:00
cvs
beff63eb32 - entered original Bochs snapshot bochs-2000_0325a.tar.gz from
ftp.bochs.com
2001-04-10 01:04:59 +00:00