Stanislav Shwartsman
9bebe91826
eliminate duplicated cpu methods by adding extra param to opcodes with no modrm
2012-02-03 10:24:59 +00:00
Stanislav Shwartsman
f09bdf353a
RDMSR can also read TSC so make it end-of-trace as well (same as RDTSC)
2011-11-24 16:03:51 +00:00
Stanislav Shwartsman
ad9bdbe550
fixed compilation failure
2011-10-21 08:06:55 +00:00
Stanislav Shwartsman
5d9bbae71c
bugfix: cant use ib2 it is overlap with disp32
2011-10-19 21:28:36 +00:00
Stanislav Shwartsman
5cc04b9955
Implemented AMDs Buldozer XOP and TBM extensions.
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XOP: few instructions are still missing, coming soon
BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
c6d07ae1b5
store modrm() for x87 in Ib() byte because x87 have no Ib()
2011-09-20 06:02:27 +00:00
Stanislav Shwartsman
50207eeb90
- Added support for AMD SSE4A emulation, the instructions can be enabled
...
using .bochsrc CPUID option.
2011-09-18 16:18:22 +00:00
Stanislav Shwartsman
e000b61cfd
make RDTSC 'end of trace' instruction - guarantee that any pair ot RDTSC/RDTSCP on same CPU do not belong to same trace (and therefore will always update time and etc) - required for Win7 Thin
2011-09-06 14:13:39 +00:00
Stanislav Shwartsman
c0f5919787
small optimization
2011-09-03 15:36:40 +00:00
Stanislav Shwartsman
8099fd9efd
implemented alternative access to CR8: AMD feature. Lock CR0 -> CR8
2011-09-03 15:22:56 +00:00
Stanislav Shwartsman
1f5e036695
lzcnt/tzcnt bmi instructions implemented
2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
c30275016e
avx2 added broadcast from register
2011-08-29 21:00:25 +00:00
Stanislav Shwartsman
6bdfbeeffa
fixed for gather VSIB calculation
2011-08-28 20:14:53 +00:00
Stanislav Shwartsman
239c5a449d
added 'locked' information to bxInstruction_c for instrumentation and other future use
2011-08-27 20:09:18 +00:00
Stanislav Shwartsman
44241a1e56
- Added support for AVX and AVX2 instructions emulation, to enable configure
...
with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
d84dbcd02b
fixed *x86 ISA extensions that enable this instruction* in ia_opcodes.h
2011-07-31 20:09:04 +00:00
Stanislav Shwartsman
e48765a511
VMX fixed, cleanups
2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
...
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
f7c6bd1134
clean code dupication
2011-06-27 19:27:49 +00:00
Stanislav Shwartsman
beafa7c88b
improved x86 hw code bp handling
2011-06-24 13:38:34 +00:00
Stanislav Shwartsman
29e3f6e762
remove trace cache disabled mode from the code. next step going to be - introducing new optimization features based on trace cache
2011-06-01 20:34:04 +00:00
Stanislav Shwartsman
a02ddb36d2
undo a change from 2 weeks ago that cause correctness failure
2011-05-06 08:03:45 +00:00
Stanislav Shwartsman
c44f82f4ac
small cleanup
2011-04-25 20:26:22 +00:00
Stanislav Shwartsman
024a1ace38
move X2APIC to be .bochsrc option, rework of the cpuid code
2011-04-21 13:27:42 +00:00
Stanislav Shwartsman
69b829a935
small fixes
2011-04-12 06:05:31 +00:00
Stanislav Shwartsman
4de76b0571
introduced victim cache for a trace cache structure.
...
Allows to significantly cut trace cache miss latenct and find data in victim cahe instead of redoding it
8 entries VC in parallel with direct map 64K entries
2011-03-25 23:06:34 +00:00
Stanislav Shwartsman
7664c55b08
first fixups after AVX
...
(and for AVX)
2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
...
many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
acb83acfa7
Fixed decoding of CRC32 instr
2011-02-26 20:43:11 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
2d3f3668c7
Fixed IRET 64-bit mode bug
...
Support for 32 float copare methods for AVX
ckeanups in fetchdecode
2011-02-13 06:10:11 +00:00
Stanislav Shwartsman
12005d92cf
split more SSE ops
2011-01-21 19:46:44 +00:00
Stanislav Shwartsman
0de2b305bc
split SSE opcode
2011-01-21 19:21:16 +00:00
Stanislav Shwartsman
a31103e7d8
optimize fetchdecode tables - part2
2011-01-21 16:07:51 +00:00
Stanislav Shwartsman
fbc9b8b190
phase1 of opcode tables optimization
2011-01-20 16:24:42 +00:00
Stanislav Shwartsman
8c5c078b13
optimize sse and mmx code
2011-01-16 20:42:28 +00:00
Stanislav Shwartsman
a80b44b6db
split more sse ops
2011-01-09 20:18:02 +00:00
Stanislav Shwartsman
a1bc92a46b
split more SSE opcodes
2011-01-08 11:20:29 +00:00
Stanislav Shwartsman
205351f44e
Split R/M all SSE fetchdecode tables
...
- next step optimize tables
2011-01-08 09:53:52 +00:00
Stanislav Shwartsman
f9f868247a
split more SSE ops
2010-12-30 20:35:10 +00:00
Stanislav Shwartsman
25b1e2e58d
split more SSE ops
2010-12-26 20:41:47 +00:00
Stanislav Shwartsman
c005444d5b
split more SSE opcodes
2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
040a8e1a3a
split bunch of SSE opcodes
2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
43600f3756
complete rework of SSE code
...
next step - split all SSE opcodes by ModC0
2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
29a674e520
split rd/wr CR opcodes for simplicity
2010-12-19 22:36:19 +00:00
Stanislav Shwartsman
d60b7c0919
rename accessor for opcodeReg() in instruction
2010-12-06 21:45:56 +00:00
Stanislav Shwartsman
49c85b07f6
Fixed address size wrap
2010-10-18 22:19:45 +00:00
Stanislav Shwartsman
f655e33779
imm mode2 could be only with imm_mode1
2010-09-25 10:17:04 +00:00
Stanislav Shwartsman
75f2ae9c18
fetchdecode simplification rework
2010-09-25 09:55:40 +00:00
Stanislav Shwartsman
369aba757d
style change
2010-09-23 20:38:02 +00:00
