mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
9,385 Commits 11 Branches 185 Tags 48 MiB
deaf58b130
Commit Graph

63 Commits

Author SHA1 Message Date
Stanislav Shwartsman
9261b2fa14 removed param_names.h include where not needed anymore 2012-01-07 17:54:19 +00:00
Stanislav Shwartsman
7defa74261 cleaned up code duplication in CPUDB classes 2012-01-07 17:06:03 +00:00
Stanislav Shwartsman
a804adac46 fixed compilation err with SMP enabled 2012-01-07 16:45:25 +00:00
Stanislav Shwartsman
0e17f8f195 implemented AMD APIC extensions for SVM support 2012-01-04 16:06:37 +00:00
Stanislav Shwartsman
c857488ed9 Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-02 20:59:02 +00:00
Stanislav Shwartsman
810aa1b67c fixes for SVN. also turion64_tyler supports RDTSCP - include it in CPUID 2012-01-01 17:54:41 +00:00
Stanislav Shwartsman
560e3ca254 compilation fix for smp=0 2011-12-30 18:55:19 +00:00
Stanislav Shwartsman
cee8a3b9ef AMD's core has special 0x80000008.ecx value 2011-12-30 18:53:41 +00:00
Stanislav Shwartsman
088ab4832f turion64 tyler supports cmpxchg16b 2011-12-30 18:46:46 +00:00
Stanislav Shwartsman
abda3a967c added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
Stanislav Shwartsman
2b854cb101 added basic (very basic) SVM CPUID into generic_cpuid module 2011-12-28 21:54:51 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
c74f590077 implemented TSC-Deadline APIC timer mode 2011-11-21 12:51:50 +00:00
Stanislav Shwartsman
e4bd200119 do not report TSC Deadline for Sandy Bridge CPUID - not implemented yet 2011-11-20 18:25:39 +00:00
Stanislav Shwartsman
9be8552b80 - Implemented VM Functions support and EPTP-Switching VM Functions 
- Added VMEXIT conditions for INVPCID instruction

Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
 2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
314171bb56 fixed compilation w/o AVX 2011-10-09 13:56:39 +00:00
Stanislav Shwartsman
8ada4ce5e4 added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
Stanislav Shwartsman
f0d9f8fab7 added some comments 2011-09-26 20:10:15 +00:00
Stanislav Shwartsman
12ad45395b enable Penryn VMX capabilities with VMX=1, VMX=2 is required for EPT and heavier stuff 2011-09-26 19:36:20 +00:00
Stanislav Shwartsman
aa96ecd98a compilation fix 2011-09-26 18:18:10 +00:00
Stanislav Shwartsman
0aadf88c07 more polishing for vmx configurability 2011-09-26 18:08:31 +00:00
Stanislav Shwartsman
c28c7f6a06 Supply real VMX capabilities together with the CPU MODEL .bochsrc option. 
So now the same single option will choose not only the CPUID flags but also VMX capabilities matching real HW machine.

Removed cpuid of core2_extreme_x9770 from the cpudb. I don't remember its VMX capabilities anyway.
There is another Penryn model in the cpudb - core2_penryn_t9600.
 2011-09-26 12:31:40 +00:00
Stanislav Shwartsman
62d0c8abf7 - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 
32-bit CPU using Bochs binary compiled with x86-64 support.

The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
 2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
e2f0880f1c support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
9f1f4781b3 fixed Sandy Bridge name in err message - it is Core i7 and not Core2 2011-09-06 19:49:22 +00:00
Stanislav Shwartsman
dfd769a102 - Fixed compilation issue with cpu-level=5 
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
 2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b syscall/sysret are not supported outside long64 mode in Intel CPUs 2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
542af0dcc1 forgot to add a file 2011-08-18 19:02:16 +00:00
Stanislav Shwartsman
b8b63ac6ea compile CPUDB to separate library 
reduce compile-time dependencies
 2011-08-18 18:55:22 +00:00
Stanislav Shwartsman
ed9b8478b5 undo RDTSC commit 2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf separate TSC to uniq feature that can be disabled in CPU configuration 2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
b0d7ffeb90 fixed compilation 2011-08-16 20:07:34 +00:00
Stanislav Shwartsman
a03e0266fb added yonah CPUID to cpudb. remove bxversion.h from dep files 2011-08-16 19:58:56 +00:00
Stanislav Shwartsman
0bc93fdc59 added pentium mmx to cpudb. for now only can be enabled when cpu-level=5 2011-08-16 19:04:36 +00:00
Stanislav Shwartsman
290d3bf6ad typofix 2011-08-12 18:09:24 +00:00
Stanislav Shwartsman
8962cfddde re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc 2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
7af5dccdcf fixed compilation issue 2011-08-11 19:45:21 +00:00
Stanislav Shwartsman
d0344a1b84 added Id Revision to new files 2011-08-11 18:17:45 +00:00
Stanislav Shwartsman
6344c6a719 Added P2 Klamath CPUID + some code reorg again 2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
1b27438146 cleanups + small code reorg 2011-08-10 20:31:29 +00:00
Stanislav Shwartsman
360481b391 infastructure for RDMSR/WRMSR control for cpuid class 
now the order is going to be:

1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
 2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
c6c94a79da dos2unix for generic_cpuid.cc 
fixed xsave leaf CPUID (again)
added one more CPUID configuration: Intel Mobile Core 2 Duo T9600
 2011-08-08 18:20:29 +00:00
Stanislav Shwartsman
20becdfbe7 fix compilation errors 2011-08-05 07:22:43 +00:00
Stanislav Shwartsman
b6e37b818d small changes 2011-08-04 17:35:08 +00:00
Stanislav Shwartsman
1068b4bd8c cleanup 2011-08-03 21:46:46 +00:00
Stanislav Shwartsman
5ffb201184 fixed CPU leaf 0xD 2011-08-03 21:23:08 +00:00
Stanislav Shwartsman
1adda7bf64 Fixed MWAIT leaf CPUID - required for Fedora15 startup 2011-08-03 20:29:24 +00:00
Stanislav Shwartsman
5451be2676 remove duplicated code 2011-08-03 18:09:07 +00:00
Stanislav Shwartsman
9162c0dc2a dos2unix 2011-08-03 17:50:23 +00:00