Stanislav Shwartsman
54831068df
implement RDMSRLIST/WRMSRLIST instructions (+related VMX extensions) ( #176 )
2023-12-16 21:59:34 +02:00
Shwartsman
e68ae599af
added comments and consts for CPUID definitions
2023-12-16 10:10:48 +02:00
Stanislav Shwartsman
2e89b9bcba
implemented WAITPKG instruction set ( #150 )
...
still missing : UMWAIT/TPAUSE should set CF flag if it was using OS
deadline and woken up after deadline (i.e. not from monitored store)
also not clear in the spec: should UWAITX/TPAUSE always wait until
deadline due to 'while(tsc<deadline)' statement ?
+include small fixes for AMD's MONITORX/MWAITX
2023-12-01 18:00:03 +02:00
Stanislav Shwartsman
280303d76c
initial code for UINTR implementation ( #138 )
...
First step into implementing UINTR - User Level Interrupts ISA extension
To be continued
---------
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
2023-11-25 16:43:47 +02:00
Stanislav Shwartsman
c1c102ab04
coding style, cleanups and optimizations
2023-11-19 20:31:05 +02:00
Stanislav Shwartsman
dd7d4dbd82
implement SERIALIZE instruction
...
enable CPUID reporting for all recently added ISA extensions
2023-10-12 14:46:27 +03:00
Stanislav Shwartsman
3a20495db8
implemented WRMSRNS extension - Non Serializing version of WRMSR opcode
2022-10-02 22:16:02 +03:00
Stanislav Shwartsman
1e4f1624c8
remove trailing whitespace from source files
2022-08-23 21:46:04 +03:00
Stanislav Shwartsman
f90e5f4f44
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
...
Only missing items (to be added soon):
- Supervisor Shadow Stack EPT Control is not implemented yet
- SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
7833a82347
fixed bug in instruction decoding - regression before release
2019-11-22 17:46:54 +00:00
Stanislav Shwartsman
f0245b5f2b
introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode
2019-10-14 06:40:19 +00:00
Stanislav Shwartsman
3e007fbdea
fixed copy-pasted issue with decoding
2019-02-17 21:54:38 +00:00
Stanislav Shwartsman
c3f7a34cf5
fixed copy-pasted issue with decoding
2019-02-17 21:41:45 +00:00
Stanislav Shwartsman
3da93728b3
split some opcode reference tables in new decoder between x86-64 and 32 for better perf
2019-02-17 21:22:54 +00:00
Stanislav Shwartsman
cd79d22113
fixes for 32-bit mode only compilation
2019-02-16 19:42:04 +00:00
Stanislav Shwartsman
4f625b23e0
enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore
2019-02-16 15:23:24 +00:00
Stanislav Shwartsman
2f3c9d3c8c
correct disasm for movsxd opcode
2017-12-13 18:44:13 +00:00
Stanislav Shwartsman
862e817884
fixed typo caused compilation err
2017-03-28 19:13:20 +00:00
Stanislav Shwartsman
b7b0165d3c
new naming convention for UD opcodes
2017-03-28 19:00:00 +00:00
Stanislav Shwartsman
2b79061127
Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model
2017-03-26 19:14:15 +00:00
Stanislav Shwartsman
411ea954b4
implemented CLZERO instruction from AMD Ryzen CPU
2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
be4c6c7ae5
SMAP opcodes are No-SSE-Prefix
2017-03-16 16:20:58 +00:00
Stanislav Shwartsman
521d2d10c4
correctly fixed x32 emu compilation err + bugfix for AVX decoder
2017-01-11 20:51:58 +00:00
Stanislav Shwartsman
90c4cb31c5
add SVN header to newly added files
2017-01-10 20:16:24 +00:00
Stanislav Shwartsman
10eb193e01
step 1 of rewrite Bochs decoder: legacy decoder tables done. TODO: avx/evex decoder tables, merge decoder and disasm together
2017-01-10 20:15:17 +00:00
