Stanislav Shwartsman
d766cc8112
implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition
2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
773f1b7e42
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
3a033fa6db
implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen)
2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
f6af0443bb
small optimization and elimination of several defines from cpu.h - replace by inline functions and const variables
2015-07-13 20:24:14 +00:00
Stanislav Shwartsman
1e1c893041
introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it
2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
7a3e340e6d
implement memory type calculation by mtrr. todo: memory type from page tables
2015-02-20 21:50:59 +00:00
Stanislav Shwartsman
e16c6eb30c
preparations and interface definition for memory type support
2015-02-19 20:23:08 +00:00
Stanislav Shwartsman
f01891faa2
fixed compilation err with perfmon disabled
2014-11-07 13:15:54 +00:00
Stanislav Shwartsman
54a009ccf9
update CHANGES. added BX_INFO prints related to Perfmon usage
2014-10-15 19:04:28 +00:00
Stanislav Shwartsman
29efae3be3
adjust (c) in several files
2014-08-31 20:05:25 +00:00
Stanislav Shwartsman
5eb781e45f
cleanup after cpu features interface rework
2014-08-31 19:22:41 +00:00
Stanislav Shwartsman
3fbdf7ff03
do not recognize MTRR MSRs when mtrr is not enabled
2013-04-17 19:59:56 +00:00
Stanislav Shwartsman
025fb15461
properly handle RDMSR/WRMSR of MSR_PAT when PAT feature is disabled
2013-04-11 19:41:54 +00:00
Stanislav Shwartsman
48d7fa3786
fixed code duplication, mainly in vmx/svm code
2012-12-26 21:59:16 +00:00
Stanislav Shwartsman
744001e35e
Implemented VMX APIC Registers Virtualization and VMX Virtual Interrupt Delivery emulation
...
Bugfix: VMX: VmEntry should do TPR Virtualization (TPR Shadow + APIC Access Virtualization case is affected) and even could possibly cause TPR Threshold VMEXIT
2012-10-26 18:43:53 +00:00
Stanislav Shwartsman
9b65cae026
make WRMSR end-of-trace instruction
2012-10-25 16:49:22 +00:00
Stanislav Shwartsman
4273b41d00
fixed write to apicbase when in x2apic mode
2012-10-25 16:09:34 +00:00
Stanislav Shwartsman
2f3c7ff8e4
implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14
...
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc
Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
e0729e32b8
fixed bug 3548108 VMEXIT instruction length Not always getting updated
2012-07-26 16:03:26 +00:00
Stanislav Shwartsman
ffc5e4bf2d
optimize x2apic reg write
2012-05-12 19:07:18 +00:00
Stanislav Shwartsman
39c14ef0d1
Implemented EPT A/D extensions support.
...
Bochs is fully aligned with the latest published revision of
Intel Architecture Manual (revision 043) now.
2012-05-02 18:11:39 +00:00
Stanislav Shwartsman
f5d55f5eb6
- Implemented Task Switch intercept in SVM, cleanup in task switch handling code
...
- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
3c0d712146
SVM fixes
2011-12-31 13:58:55 +00:00
Stanislav Shwartsman
46d8a5894e
removed bad RDMSR/WRMSR check which disabled access to AMD extended MSRs
2011-12-31 12:37:35 +00:00
Stanislav Shwartsman
0a14f08f16
completing SVM coding, missed - CPUID, extended APIC
2011-12-28 16:12:28 +00:00
Stanislav Shwartsman
7f5f917a34
more SVM implementation
2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
6ae86a059b
firt cleanup in SVM code. added intercept check for MSR and IO
2011-12-26 19:57:39 +00:00
Stanislav Shwartsman
c74f590077
implemented TSC-Deadline APIC timer mode
2011-11-21 12:51:50 +00:00
Stanislav Shwartsman
9be8552b80
- Implemented VM Functions support and EPTP-Switching VM Functions
...
- Added VMEXIT conditions for INVPCID instruction
Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
275194fb32
#GP on reading VMX_EPT_VPID_CAP MSR when EPT and VPID disabled
2011-09-26 20:36:26 +00:00
Stanislav Shwartsman
62d0c8abf7
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
...
32-bit CPU using Bochs binary compiled with x86-64 support.
The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
dfd769a102
- Fixed compilation issue with cpu-level=5
...
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b
syscall/sysret are not supported outside long64 mode in Intel CPUs
2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
fa930961c2
small optimization
2011-08-23 21:25:34 +00:00
Stanislav Shwartsman
002e7a3818
MSR_TSC_AUX is not available without RDTSCP
2011-08-21 19:09:35 +00:00
Stanislav Shwartsman
ed9b8478b5
undo RDTSC commit
2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf
separate TSC to uniq feature that can be disabled in CPU configuration
2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
e50e187128
#GP on EFER access when not supported
2011-08-14 20:41:46 +00:00
Stanislav Shwartsman
f15bc6cf75
support for NX outside of x86-64.
...
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
360481b391
infastructure for RDMSR/WRMSR control for cpuid class
...
now the order is going to be:
1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
0171324877
small favor to VMX OFF for code that compiled with VMX ON
...
avoid function call when not in vmx guest.
2011-08-09 20:50:51 +00:00
Stanislav Shwartsman
e48765a511
VMX fixed, cleanups
2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
78327d3e5e
First step toward completely configurable CPU.
...
Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
...
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
024a1ace38
move X2APIC to be .bochsrc option, rework of the cpuid code
2011-04-21 13:27:42 +00:00
Volker Ruppert
c78026a9a2
- deleted executable properties from source files
2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
acd320699d
small cleanups
2011-03-14 06:25:54 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
5ea2591cd9
fixes
2010-10-07 20:40:01 +00:00
Stanislav Shwartsman
32ff6e4879
MSR BX_DEBUG prints
2010-05-16 13:56:22 +00:00