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295 Commits

Author SHA1 Message Date
Stanislav Shwartsman
f5d55f5eb6 - Implemented Task Switch intercept in SVM, cleanup in task switch handling code 
- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
 2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
8d698c7087 fixed compilation err ith cpu-level=5 and cleanups 2012-01-09 20:52:15 +00:00
Stanislav Shwartsman
fe6328d18c correctly enable SVM support in internal CPU features list 2011-12-31 12:58:20 +00:00
Stanislav Shwartsman
7f5f917a34 more SVM implementation 2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
6ae86a059b firt cleanup in SVM code. added intercept check for MSR and IO 2011-12-26 19:57:39 +00:00
Stanislav Shwartsman
8b4a2c2034 implemented some more intercepts. 
fixed compilation without SVM
 2011-12-26 16:33:13 +00:00
Stanislav Shwartsman
bfcbb81602 SVM: 
- IO intercept is not implemented yet
 - MSR intercept is not implemented yet

VMX:
 Fixed Bochs PANIC crash when doing I/O access crossing VMX I/O permission bitmaps.
 This can happen because access_physical_read and access_physical_write cannot access memory cross 4K boundary.
 2011-12-25 22:09:31 +00:00
Stanislav Shwartsman
01080243d4 complation fix 2011-12-25 19:58:21 +00:00
Stanislav Shwartsman
a44c1b8e1e SVM and VMX share tsc offset code 2011-12-25 19:53:23 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
e7ed8aca5c move inhibit interrrupts functionality to icount interface 2011-12-21 06:17:45 +00:00
Stanislav Shwartsman
c28c7f6a06 Supply real VMX capabilities together with the CPU MODEL .bochsrc option. 
So now the same single option will choose not only the CPUID flags but also VMX capabilities matching real HW machine.

Removed cpuid of core2_extreme_x9770 from the cpudb. I don't remember its VMX capabilities anyway.
There is another Penryn model in the cpudb - core2_penryn_t9600.
 2011-09-26 12:31:40 +00:00
Stanislav Shwartsman
62d0c8abf7 - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 
32-bit CPU using Bochs binary compiled with x86-64 support.

The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
 2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
1b9f286945 - New way of CPUs scheduling in SMP mode brings up to 50% speedup to the 
SMP emulation. New implementation uses dynamic CPU quantum value and takes
   full advantage of the trace cache. Each emulated processor will execute
   the whole trace before switching to the next processor.
 * It is also safe to use large (up to 16 instructions) quantum values for
   the SMP emulation now and improve performance even further.

The same merge also completely fixes SF bug :
  [3312237] stepN command might be not working properly

Handlers chaining speedups are also supported with SMP emulation now.
 2011-09-22 19:38:52 +00:00
Stanislav Shwartsman
96cedbc756 continue handlers-chaining optimization: update time once per trace and not for every instruction 2011-09-06 15:35:39 +00:00
Stanislav Shwartsman
fb9da23f9b syscall/sysret are not supported outside long64 mode in Intel CPUs 2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
371dc200fc Remove the 'trace' debug feature fro the main stream (which now runs with handlers chaining) and this way reduce each handler size. 
Another 3% speedup on WinXP boot on top of handlers chaining + reduction of Bochs binary size by 45K.
 2011-08-21 17:04:21 +00:00
Stanislav Shwartsman
4a3209ae31 Increase cpu param length (exceeded with new icount variable) 
CHECK_MAX_INSTRUCTIONS is not needed for debugger anymore.
Next step: eliminate it for SMP as well and remove cpu_loop parameter.
 2011-08-17 20:00:51 +00:00
Stanislav Shwartsman
b69f728246 Fixed internal debugger part of the bug: 
#3312237 stepN command might be not working properly
The problem still can be exists for SMP.
 2011-08-17 19:51:32 +00:00
Stanislav Shwartsman
6606c62439 cr4 available since Pentium only 2011-08-16 16:49:04 +00:00
Stanislav Shwartsman
8962cfddde re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc 2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
7af5dccdcf fixed compilation issue 2011-08-11 19:45:21 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
1b27438146 cleanups + small code reorg 2011-08-10 20:31:29 +00:00
Stanislav Shwartsman
2ee0029749 extract ffxsr support to separate CPU feature 2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
1d89709e62 Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). 
Reimplemented CPUDB using pure C macros magic.
Fixed compilation errors when compiling with SMP on.
 2011-07-31 18:43:46 +00:00
Stanislav Shwartsman
6e6db04b8f Fixed compilation errors, dos2unix, added missed p3_katmai.txt 2011-07-31 14:56:45 +00:00
Stanislav Shwartsman
5e291e0860 Added Athlon64 Clawhammer CPUID to CPUDB 2011-07-30 21:28:16 +00:00
Stanislav Shwartsman
fefa4d5e5b added PIII Katmai to CPUDB 2011-07-30 14:30:35 +00:00
Stanislav Shwartsman
4ac67ec386 compilation when cu_level < 4 2011-07-29 15:24:32 +00:00
Stanislav Shwartsman
1a051f9f00 Added several predefined CPUs that can be selected from .bochsrc using new CPU::MODEL option. 
Selecting CPU MODEL from .bochsrc automatically chooses real HW CPUID and also configures Bochs emulator to emulate this specific CPU including all its features only.
Supported CPUs to choose from:
	core2_extreme_x9770
	corei7_sandy_bridge_2600K
	p4_prescott_celeron_336
 2011-07-29 15:03:54 +00:00
Stanislav Shwartsman
78327d3e5e First step toward completely configurable CPU. 
Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
 2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
81f6a283e2 trim cpuid info from save/restore tree 2011-07-27 14:16:51 +00:00
Stanislav Shwartsman
cddd1e3758 MONITOR/MWAIT: Do monitor on cache line granularity only + bugfix with possible TLB caching of monitored line 2011-07-18 21:44:22 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
909e750549 Implemented VMX preemption timer VMEXIT control (patch by Jianan Hao) 2011-07-03 15:59:48 +00:00
Stanislav Shwartsman
beafa7c88b improved x86 hw code bp handling 2011-06-24 13:38:34 +00:00
Stanislav Shwartsman
024a1ace38 move X2APIC to be .bochsrc option, rework of the cpuid code 2011-04-21 13:27:42 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
63fe52f601 accessors for DR6 and DR7 fields 2011-03-15 20:20:15 +00:00
Stanislav Shwartsman
aff763349d Fixed save/restore of segments in real mode (valid bit was corrupted) 2011-03-12 09:56:43 +00:00
Stanislav Shwartsman
93e152ef1a no need to read ignore_bad_msrs on every reset 2011-03-05 18:54:23 +00:00
Stanislav Shwartsman
3b8903e19d there is no need to duplicate ignore_bad_msrs in param tree, this knob is loaded from options anyway 2011-03-05 18:47:48 +00:00
Stanislav Shwartsman
2d1d41e731 CPUID is not available when cpu-level=3 2011-02-25 16:27:01 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
43600f3756 complete rework of SSE code 
next step - split all SSE opcodes by ModC0
 2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
c7017b1c05 simplification 2010-12-19 21:41:15 +00:00
Stanislav Shwartsman
4a85a8680e SSE optimization 2010-12-19 07:06:40 +00:00
Stanislav Shwartsman
1047acb2cc rename SSE register param - prepare for wide SSE register (AVX) 2010-12-06 21:52:41 +00:00
Stanislav Shwartsman
eaa2e0e0ea [PATCH] cpu/init.cc: proper CPL restore in after_restore_statE 2010-06-04 20:31:04 +00:00