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346 Commits

Author SHA1 Message Date
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
112e61f1c3 coding style: avoid goto, magic constants and defines which could be replaced by enums 2019-12-15 18:45:04 +00:00
Stanislav Shwartsman
c117208bbf extending fix to AMD SVM 2019-12-13 18:47:51 +00:00
Stanislav Shwartsman
1968cdf248 proposed fix for SF issue #547 vmcshostptr not invalidated after memory swapped out 2019-12-13 18:31:43 +00:00
Stanislav Shwartsman
4b66fecaad split Bochs CPU TLB to DTLB and ITLB to avoid aliasing conflicts between them. ~5% speedup measured 2019-12-09 18:37:02 +00:00
Stanislav Shwartsman
8befc3bf82 make separate class for TLB to be used in CPU class. preparation to DTLB and ITLB split of TLB structure 2019-12-09 16:49:51 +00:00
Stanislav Shwartsman
96e2c50bef applying SF patch #545 Speling fixes 2019-12-09 16:29:23 +00:00
Stanislav Shwartsman
951361a3a5 bugfix: PKRU should affect only user-mode memory accesses (bug in page translation) 2019-12-04 17:27:57 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
7a183ab520 fixed PDE4M reserved bits checking if physical address wider than 40 bit 2018-11-22 11:51:33 +00:00
Stanislav Shwartsman
cf41679b53 closing bug report: Missing TLB_flush on VMX_VMEXIT_EPT_VIOLATION 2018-08-30 20:18:27 +00:00
Stanislav Shwartsman
965bcc2606 support 64-bit in 'info tab' debugger command and also speed it up significantly 2018-08-14 08:09:09 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
2bca4cc310 improve debug print for SPP access 2018-01-27 21:25:46 +00:00
Stanislav Shwartsman
afc2ee6bfd Implemented SPP: EPT-Based Subpage Protection. Cleaned code duplication between FXSAVE/FXRSTORE and XSAVE/XRSTOR (save/restore of SSE code is the same) 2018-01-27 21:20:33 +00:00
Stanislav Shwartsman
a9ac81e092 convert defines to const and enum in paging.cc 2018-01-27 19:31:39 +00:00
Stanislav Shwartsman
7b2a8bb340 added missing EPT misconfig condition check 2016-12-10 05:06:59 +00:00
Stanislav Shwartsman
12ece81e19 look only on valid tlb entries in check_addr_in_tlb_buffers and tlb invalidation methods 2016-05-06 06:57:00 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
cd2129ec3b avoid calling prefetch() each time when linking traces cross page 2015-10-09 05:33:44 +00:00
Stanislav Shwartsman
8d13b61319 implemented TSC Scaling VMX feature according to timestamp-counter for virtualization whitepaper published by Intel 2015-09-30 18:44:01 +00:00
Stanislav Shwartsman
ad52e15860 added few tlb specific cpustat counters 2015-09-28 19:09:32 +00:00
Stanislav Shwartsman
8232928096 small code optimization and simplification 2015-09-23 19:25:07 +00:00
Stanislav Shwartsman
c44cb6ed81 more cases applicable for BX_TLB_ENTRY_OF 2015-09-22 20:10:22 +00:00
Stanislav Shwartsman
be4b73c6d2 extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class 2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
b468316250 re-style old resolve macros after resolve function inlining 2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
9f18573740 Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only) 2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
0d79c5f986 Implemented Page Modification Logging VMX feature 2015-05-06 19:55:44 +00:00
Stanislav Shwartsman
9be2f07d54 fix compilation err when SVM is enabled 2015-04-21 08:20:28 +00:00
Stanislav Shwartsman
c360ddf60c correctly report memory type for EPT page table accesses 
TODO: support memory type for guest physical access under EPT
TODO: support memory type for SVM nested paging 
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-23 20:27:36 +00:00
Stanislav Shwartsman
05635a9534 call correctly resolve_memtype function 2015-03-21 20:28:22 +00:00
Stanislav Shwartsman
56323b2806 bugfixes 2015-03-21 20:15:57 +00:00
Stanislav Shwartsman
a55c5e4eb8 correctly report memory type for page table accesses in x86 mode (not in EPT or SVM nested paging yet) 
TODO: support memory type with EPT / nested paging
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-21 20:08:58 +00:00
Stanislav Shwartsman
e79185b0a0 refactor memtype methods 2015-03-02 20:51:59 +00:00
Stanislav Shwartsman
36f7bf0ba6 fixed ept memtype printout 2015-03-01 21:04:34 +00:00
Stanislav Shwartsman
8134dc67af supporting memory type provided by page tables with PCD,PWT and PAT bits 
TODO: support memory type with EPT
TODO: support memory type for intermediate page table accesses
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-01 20:55:23 +00:00
Stanislav Shwartsman
53041981f7 supply PAT required memory type bits through new combined access interface 2015-02-28 14:06:04 +00:00
Stanislav Shwartsman
25b02dac4b code reorg before PAT memory type support 2015-02-28 14:01:11 +00:00
Stanislav Shwartsman
1e1c893041 introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it 2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
2bad0d0d12 fixed link error with debugger enabled, small speed optimization 2015-02-23 19:55:55 +00:00
Stanislav Shwartsman
0917d12e8b memory type report for physical accesses and RMW acccesses. todo: consider also pat 2015-02-22 21:26:26 +00:00
Stanislav Shwartsman
7a3e340e6d implement memory type calculation by mtrr. todo: memory type from page tables 2015-02-20 21:50:59 +00:00
Stanislav Shwartsman
e16c6eb30c preparations and interface definition for memory type support 2015-02-19 20:23:08 +00:00
Volker Ruppert
2ec57b8a6b Fixed some more C++11 warnings. 2014-12-18 17:52:40 +00:00
Stanislav Shwartsman
8d1e3b2ac1 Added statistics collection infrastructure in Bochs and 
implemented important CPU statistics which were used for Bochs CPU model performance analysis.
old statistics code from paging.cc and cpu.cc is replaced with new infrastructure.

In order to enale statitics collection in Bochs CPU:

- Enable statistics @ compilation time in cpu/cpustats.h
- Dump statistics periodically by adding -dumpstats N into Bochs command line
 2014-10-14 15:59:10 +00:00
Stanislav Shwartsman
5eb781e45f cleanup after cpu features interface rework 2014-08-31 19:22:41 +00:00
Stanislav Shwartsman
816f5cc2d7 fixed massive code duplication 2014-07-03 06:40:42 +00:00
Stanislav Shwartsman
776cabf4fe move canonical check of high part of page split access to another function to fix code duplication 2013-12-21 21:56:55 +00:00
Stanislav Shwartsman
a85a9081b7 use shorter opcode names in the debug prints (skip the BX_IA_ prefix) 2013-12-02 20:06:59 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00