Commit Graph

48 Commits

Author SHA1 Message Date
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
ac442009aa lazy flags code small refactoring 2017-10-15 22:01:32 +00:00
Stanislav Shwartsman
cc694377b9 Standartization of Bochs instruction handlers.
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions.
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation.
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
c3a31d3cf0 applied patch bochs-110423-builtinbswap.patch 2011-04-25 15:20:27 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
59eb1200c2 fixed IMUL eflags 2010-04-15 19:50:57 +00:00
Stanislav Shwartsman
d8f65d66e0 IDIV64 fix 2010-03-21 06:53:14 +00:00
Stanislav Shwartsman
cffe32dd2c remove unused param from exception() call 2010-03-14 15:51:27 +00:00
Stanislav Shwartsman
70dc124b3a 1st step of moving CPU options to runtime 2010-02-24 19:27:51 +00:00
Stanislav Shwartsman
bd60e0264c change Copyright to Bochs Project 2009-12-04 16:53:12 +00:00
Stanislav Shwartsman
5ab53ac4b0 cleanup + small optimization 2009-10-27 18:30:13 +00:00
Stanislav Shwartsman
4dd73f2ebe fixed CF/OF flags 2009-10-24 17:23:19 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
b61017e5b6 Split more opcodes using new LOAD technique 2008-08-10 21:16:12 +00:00
Stanislav Shwartsman
5dd02b26e3 Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before 2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
5b4c29e2de Fixed warnings found by icc compiler 2008-06-17 20:23:16 +00:00
Stanislav Shwartsman
7215607df2 - Fixed missed #DE exception in x86-64 IDIV instruction 2008-05-24 10:26:03 +00:00
Stanislav Shwartsman
ec1ff39a5f Splitted memory access methods for 32 and 64-bit code.
The 64-bit code got >10% speedup, the 32-bit code also got about 2% because laddr cacluation optimization
2008-05-10 18:10:53 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
d891f0d8ec Fixed more VC2008 warnings - hopefully last ones 2007-12-30 17:53:12 +00:00
Stanislav Shwartsman
79fc57dec8 Fixed more VCPP2008 warnings 2007-12-26 23:07:44 +00:00
Stanislav Shwartsman
838fb2a048 Fixing V2008 warnings - they found a bug in sse_pfp.cc ! 2007-12-23 17:21:28 +00:00
Stanislav Shwartsman
5d4e32b8da Avoid pointer params for every read_virtual_* except 16-byte SSE and 10-byte x87 reads 2007-12-20 20:58:38 +00:00
Stanislav Shwartsman
d54d537f81 One more step for lazy flags optimization 2007-12-06 16:57:59 +00:00
Stanislav Shwartsman
1a55835155 Optimize lazy flags for MUL/IMUL 2007-11-29 21:45:10 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :)
Also split EqId G1 group for x86-64
2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
2548c05537 Enable SSE4_2 in CPUID 2007-10-01 21:08:26 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
400b7094c6 Commit patch by kuma neko [yuubyou@gmail.com]
64-bit IDIV uses unsigned overflow test
2005-05-13 14:15:35 +00:00
Stanislav Shwartsman
5701f62a42 Fix compiler warnings with -wall 2005-02-03 18:43:23 +00:00
Stanislav Shwartsman
75006eed8a Fix MUL/IMUL instructions flags handling 2004-08-31 19:43:58 +00:00
Stanislav Shwartsman
016207b222 Commented problematic check in misc_mem.cc
Implemnted lazy-flags and undocumented flags handling for IMUL instructions
2004-08-30 21:47:24 +00:00
Stanislav Shwartsman
f2294e7c29 LAZY-FLAGS for MUL instructions
undocumented flags handling for MUL instructions
2004-08-26 20:37:50 +00:00
Stanislav Shwartsman
1f5aa2696f Fix compilation errors ;) 2004-08-18 21:29:07 +00:00
Stanislav Shwartsman
729e0abd2a Fixed bug [ 912496 ] IDIV can cause simulator divide error 2004-08-18 19:27:52 +00:00
Stanislav Shwartsman
f2dc00dda3 merge patch
[ 904549 ] imul gives incorrect result in long mode
2004-04-07 19:46:13 +00:00
Stanislav Shwartsman
bb1271cab6 little bit clean 64b code 2004-04-07 19:23:06 +00:00
Stanislav Shwartsman
6fe8e9260b remove redundant CPU LEVEL checks for x86-64 2003-12-29 21:47:36 +00:00
Bryce Denney
0a7cb3a43c - apply patch.ifdef-disabled-options. Comments from that patch are below:
For a whole lot of configure options, I put #if...#endif around code that
  is specific to the option, even in files which are normally only compiled
  when the option is on.  This allows me to create a MS Visual C++ 6.0
  workspace that supports many of these options.  The workspace will basically
  compile every file all the time, but the code for disabled options will
  be commented out by the #if...#endif.

  This may one day lead to simplification of the Makefiles and configure
  scripts, but for the moment I'm leaving Makefiles and configure scripts
  alone.

  Affected options:
    BX_SUPPORT_APIC (cpu/apic.cc)
    BX_SUPPORT_X86_64 (cpu/*64.cc)
    BX_DEBUGGER (debug/*)
    BX_DISASM (disasm/*)
    BX_WITH_nameofgui (gui/*)
    BX_SUPPORT_CDROM (iodev/cdrom.cc)
    BX_NE2K_SUPPORT (iodev/eth*.cc, iodev/ne2k.cc)
    BX_SUPPORT_APIC (iodev/ioapic.cc)
    BX_IODEBUG_SUPPORT (iodev/iodebug.cc)
    BX_PCI_SUPPORT (iodev/pci*.cc)
    BX_SUPPORT_SB16 (iodev/sb*.cc)

Modified Files:
  cpu/apic.cc cpu/arith64.cc cpu/ctrl_xfer64.cc
  cpu/data_xfer64.cc cpu/fetchdecode64.cc cpu/logical64.cc
  cpu/mult64.cc cpu/resolve64.cc cpu/shift64.cc cpu/stack64.cc
  debug/Makefile.in debug/crc.cc debug/dbg_main.cc debug/lexer.l
  debug/linux.cc debug/parser.c debug/parser.y
  disasm/dis_decode.cc disasm/dis_groups.cc gui/amigaos.cc
  gui/beos.cc gui/carbon.cc gui/macintosh.cc gui/rfb.cc
  gui/sdl.cc gui/term.cc gui/win32.cc gui/wx.cc gui/wxdialog.cc
  gui/wxmain.cc gui/x.cc iodev/cdrom.cc iodev/eth.cc
  iodev/eth_arpback.cc iodev/eth_fbsd.cc iodev/eth_linux.cc
  iodev/eth_null.cc iodev/eth_packetmaker.cc iodev/eth_tap.cc
  iodev/eth_tuntap.cc iodev/eth_win32.cc iodev/ioapic.cc
  iodev/iodebug.cc iodev/ne2k.cc iodev/pci.cc iodev/pci2isa.cc
  iodev/sb16.cc iodev/soundlnx.cc iodev/soundwin.cc
2002-11-19 05:47:45 +00:00
Bryce Denney
cec9135e9f - Apply patch.replace-Boolean rev 1.3. Every "Boolean" is now changed to a
"bx_bool" which is always defined as Bit32u on all platforms.  In Carbon
  specific code, Boolean is still used because the Carbon header files
  define it to unsigned char.
- this fixes bug [ 623152 ] MacOSX: Triple Exception Booting win95.
  The bug was that some code in Bochs depends on Boolean to be a
  32 bit value.  (This should be fixed, but I don't know all the places
  where it needs to be fixed yet.)  Because Carbon defined Boolean as
  an unsigned char, Bochs just followed along and used the unsigned char
  definition to avoid compile problems.  This exposed the dependency
  on 32 bit Boolean on MacOS X only and led to major simulation problems,
  that could only be reproduced and debugged on that platform.
- On the mailing list we debated whether to make all Booleans into "bool" or
  our own type.  I chose bx_bool for several reasons.
  1. Unlike C++'s bool, we can guarantee that bx_bool is the same size on all
     platforms, which makes it much less likely to have more platform-specific
     simulation differences in the future.  (I spent hours on a borrowed
     MacOSX machine chasing bug 618388 before discovering that different sized
     Booleans were the problem, and I don't want to repeat that.)
  2. We still have at least one dependency on 32 bit Booleans which must be
     fixed some time, but I don't want to risk introducing new bugs into the
     simulation just before the 2.0 release.

Modified Files:
    bochs.h config.h.in gdbstub.cc logio.cc main.cc pc_system.cc
    pc_system.h plugin.cc plugin.h bios/rombios.c cpu/apic.cc
    cpu/arith16.cc cpu/arith32.cc cpu/arith64.cc cpu/arith8.cc
    cpu/cpu.cc cpu/cpu.h cpu/ctrl_xfer16.cc cpu/ctrl_xfer32.cc
    cpu/ctrl_xfer64.cc cpu/data_xfer16.cc cpu/data_xfer32.cc
    cpu/data_xfer64.cc cpu/debugstuff.cc cpu/exception.cc
    cpu/fetchdecode.cc cpu/flag_ctrl_pro.cc cpu/init.cc
    cpu/io_pro.cc cpu/lazy_flags.cc cpu/lazy_flags.h cpu/mult16.cc
    cpu/mult32.cc cpu/mult64.cc cpu/mult8.cc cpu/paging.cc
    cpu/proc_ctrl.cc cpu/segment_ctrl_pro.cc cpu/stack_pro.cc
    cpu/tasking.cc debug/dbg_main.cc debug/debug.h debug/sim2.cc
    disasm/dis_decode.cc disasm/disasm.h doc/docbook/Makefile
    docs-html/cosimulation.html fpu/wmFPUemu_glue.cc
    gui/amigaos.cc gui/beos.cc gui/carbon.cc gui/gui.cc gui/gui.h
    gui/keymap.cc gui/keymap.h gui/macintosh.cc gui/nogui.cc
    gui/rfb.cc gui/sdl.cc gui/siminterface.cc gui/siminterface.h
    gui/term.cc gui/win32.cc gui/wx.cc gui/wxmain.cc gui/wxmain.h
    gui/x.cc instrument/example0/instrument.cc
    instrument/example0/instrument.h
    instrument/example1/instrument.cc
    instrument/example1/instrument.h
    instrument/stubs/instrument.cc instrument/stubs/instrument.h
    iodev/cdrom.cc iodev/cdrom.h iodev/cdrom_osx.cc iodev/cmos.cc
    iodev/devices.cc iodev/dma.cc iodev/dma.h iodev/eth_arpback.cc
    iodev/eth_packetmaker.cc iodev/eth_packetmaker.h
    iodev/floppy.cc iodev/floppy.h iodev/guest2host.h
    iodev/harddrv.cc iodev/harddrv.h iodev/ioapic.cc
    iodev/ioapic.h iodev/iodebug.cc iodev/iodev.h
    iodev/keyboard.cc iodev/keyboard.h iodev/ne2k.h
    iodev/parallel.h iodev/pci.cc iodev/pci.h iodev/pic.h
    iodev/pit.cc iodev/pit.h iodev/pit_wrap.cc iodev/pit_wrap.h
    iodev/sb16.cc iodev/sb16.h iodev/serial.cc iodev/serial.h
    iodev/vga.cc iodev/vga.h memory/memory.h memory/misc_mem.cc
2002-10-25 11:44:41 +00:00
Kevin Lawton
402d02974d Moved the EFLAGS.RF check and clearing of inhibit_mask code
in cpu.cc out of the main loop, and into the asynchronous
events handling.  I went through all the code paths, and
there doesn't seem to be any reason for that code to be
in the hot loop.

Added another accessor for getting instruction data, called
modC0().  A lot of instructions test whether the mod field
of mod-nnn-rm is 0xc0 or not, ie., it's a register operation
and not memory.  So I flag this in fetchdecode{,64}.cc.
This added on the order of 1% performance improvement for
a Win95 boot.

Macroized a few leftover calls to Write_RMV_virtual_xyz()
that didn't get modified in the x86-64 merge.  Really, they
just call the real function for now, but I want to have them
available to do direct writes with the guest2host TLB pointers.
2002-09-20 03:52:59 +00:00
Kevin Lawton
6723ca9bf4 Moved more separate fields in the bxInstruction_c into bitfields
with accessors.  Had to touch a number of files to update the
access using the new accessors.

Moved rm_addr to the CPU structure, to slim down bxInstruction_c
and to prevent future instruction caching from getting sprayed
with writes to individual rm_addr fields.  There only needs to
be one.  Though need to deal with instructions which have
static non-modrm addresses, but which are using rm_addr since
that will change.

bxInstruction_c is down to about 40 bytes now.  Trying to
get down to 24 bytes.
2002-09-18 05:36:48 +00:00
Kevin Lawton
07b0df2a8a Updated accessing of modrm/sib addressing information to
use accessors.  This lets me work on compressing the
size of fetch-decode structure (now called bxInstruction_c).

I've reduced it down to about 76 bytes.  We should be able
to do much better soon.  I needed the abstraction of the
accessors, so I have a lot of freedom to re-arrange things
without making massive future changes.

Lost a few percent of performance in these mods, but my
main focus was to get the abstraction.
2002-09-17 22:50:53 +00:00
Kevin Lawton
f05d453b6c Moved 64-bit only files from cpu64 to cpu and modified the Makefiles
accordingly.  These files cause no conflicts at all, since they
are not used in 32-bit compiles.
2002-09-13 15:53:22 +00:00