Stanislav Shwartsman
c6050a99d1
implemented AVX encoded VNNI instructions published in recent SDM - not tested yet
2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
4023b640d6
Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS)
2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
b891789c3d
implemented (experimental) TSC Adjust MSR
2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
f90e5f4f44
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
...
Only missing items (to be added soon):
- Supervisor Shadow Stack EPT Control is not implemented yet
- SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
d766cc8112
implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition
2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
4d10852c04
impemented recently published VP2INTERSECTD/Q instructions
2019-05-25 19:07:09 +00:00
Stanislav Shwartsman
54bdb24e4b
remove MOVDIRI opcode extension for now until fugured out how nicely do MOVDIR64B, they better to be both done with same CPUID feature name
2019-02-22 19:15:53 +00:00
Stanislav Shwartsman
4f625b23e0
enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore
2019-02-16 15:23:24 +00:00
Stanislav Shwartsman
9bc7faf493
dump all supported CPU fetures into Bochs log from CPUID object
2019-01-05 20:17:39 +00:00
Stanislav Shwartsman
fd15b61d94
keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM
2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
8c9f7f54b6
update CPUID definitions with recently published EAS-33 extensions document
2018-04-04 18:15:44 +00:00
Stanislav Shwartsman
8f15cfb514
fixed link err with debugger enabled
2017-12-05 19:23:41 +00:00
Stanislav Shwartsman
596b3b6eb8
reduce CPU dependencies from fetchdecode module
2017-11-25 20:20:34 +00:00
Stanislav Shwartsman
8261a91ce9
implemented GFNI instructions
2017-10-21 19:57:12 +00:00
Stanislav Shwartsman
77a62a4dcd
implemented (experimental, still untested) AVX512 VBMI2 extensions
2017-10-20 18:38:15 +00:00
Stanislav Shwartsman
5439647254
small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in
2017-10-19 21:27:25 +00:00
Stanislav Shwartsman
15ba88c195
implemented VAES/VPCLMULDQ instructions - VEX/EVEX extensions of AES/PCLMULQDQ
2017-10-19 19:12:55 +00:00
Stanislav Shwartsman
944f37b1f2
implemented AVX-512 BITALG instructions/bugfix for VPOPCNT instructions
2017-10-15 20:33:19 +00:00
Stanislav Shwartsman
0d190eec8e
implemented AVX-512 VNNI instructions
2017-10-15 19:17:07 +00:00
Stanislav Shwartsman
1abfcd39ff
implement FOPCODE and FDP deprecation CPU features
2017-05-05 20:56:13 +00:00
Stanislav Shwartsman
2b79061127
Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model
2017-03-26 19:14:15 +00:00
Stanislav Shwartsman
411ea954b4
implemented CLZERO instruction from AMD Ryzen CPU
2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
172b0106ac
imvent a bochs feature for AMD TCE and enable EFER.TCE bit
2017-03-15 22:52:08 +00:00
Stanislav Shwartsman
9bd99a604f
implemented recently announced AVX-512 extension VPOPCNT
2016-12-17 13:47:45 +00:00
Stanislav Shwartsman
7a34f00f99
extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all
2016-06-12 21:23:48 +00:00
