Stanislav Shwartsman
bfd7bb2c13
remove redundant VL512 runtime check, redundant with new decoder
2019-02-16 19:25:32 +00:00
Stanislav Shwartsman
f8ec18acd5
fix decode/disasm of AVX512-VBMI2 VPSH*D* opcodes
2019-01-27 18:52:03 +00:00
Stanislav Shwartsman
773f1b7e42
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
77a62a4dcd
implemented (experimental, still untested) AVX512 VBMI2 extensions
2017-10-20 18:38:15 +00:00
Stanislav Shwartsman
b468316250
re-style old resolve macros after resolve function inlining
2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
9f18573740
Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only)
2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
1e1c893041
introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it
2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
6ebbb886c4
implemented VPMULTISHIFTQB VBMI instruction
2014-09-26 13:19:45 +00:00
Stanislav Shwartsman
e2e6f5a62b
Update CPUID defines after recently published
...
Intel Architecture Instruction Set Extensions Programming Reference rev-021
Enable AVX-512 with all implemented extensions in generic CPUID when simd=AVX512 is supplied
implemented AVX512_IFMA532 instructions
implemented AVX512_VBMI instructions
still missing: VPMULTISHIFTQB - VBMI instruction (coming soon)
2014-09-26 12:14:53 +00:00
Stanislav Shwartsman
128137b421
avx512 bugfixes
2014-08-13 18:34:42 +00:00
Stanislav Shwartsman
4b03966176
Implemented VDBPSADBW AVX512BW instruction
...
The only missing AVX512BW/AVX512DQ opcodes are now:
"NDS.512.66.0F3A.W0 56 VREDUCEPS
NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
NDS.512.66.0F3A.W1 57 VREDUCESD"
2014-08-05 20:18:42 +00:00
Stanislav Shwartsman
b7f62cdf47
Implemented VPALIGNR AVX512BW instructions
...
The only missing AVX512BW/AVX512DQ opcodes are now:
"NDS.66.0F3A.W0 42 VDBPSADBW"
"NDS.512.66.0F3A.W0 50 VRANGEPS
NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
NDS.512.66.0F3A.W1 51 VRANGESD"
"NDS.512.66.0F3A.W0 56 VREDUCEPS
NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
NDS.512.66.0F3A.W1 57 VREDUCESD"
2014-07-26 18:59:01 +00:00
Stanislav Shwartsman
d8d4d2f0c1
Implemented VPSRLVW/VPSRAVW/VPSLLVW AVX512BW instructions
...
The only missing AVX512BW/AVX512DQ opcodes are now:
"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"
"NDS.512.66.0F3A.W0 50 VRANGEPS
NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
NDS.512.66.0F3A.W1 51 VRANGESD"
"NDS.512.66.0F3A.W0 56 VREDUCEPS
NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
NDS.512.66.0F3A.W1 57 VREDUCESD"
2014-07-25 21:15:48 +00:00
Stanislav Shwartsman
7ad7383fd2
implement 256-wide SHUFF/SHUFI ops
2014-07-25 20:08:08 +00:00
Volker Ruppert
59eac1f196
Moved AVX/EVEX stuff to a new cpu subfolder and updated build system
...
TODO: update MVSC workspace files
2014-07-25 08:35:06 +00:00
