Stanislav Shwartsman
87103c2437
Support for disasm of MOVBE Intel Atom(R) instruction
2008-08-11 17:55:57 +00:00
Stanislav Shwartsman
a85dfc7617
Added disasm for AES instructions
2008-05-25 15:42:26 +00:00
Stanislav Shwartsman
64f2489afb
Correctly implement opcode group G11 i.e. instructions C6 and C7 should @UD when modrm nnn field != 0 (1st instr in the group
2008-04-24 21:52:28 +00:00
Stanislav Shwartsman
0609d7e7ce
Handle undocumented FPU opcodes
2008-04-21 14:17:48 +00:00
Stanislav Shwartsman
405fcfd75d
Reorganize 3-byte opcode tables - bigger tables but easier to maintain them
2008-02-29 03:02:03 +00:00
Stanislav Shwartsman
8615022962
Added first stubs for XSAVE/XRESTOR implementation
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Disassemble XSAVE/XRSTOR instructions (4 instructions)
Update CHANGES - a bit speculatively
2008-02-12 22:41:39 +00:00
Stanislav Shwartsman
eebd96e2d7
another whitespace cleanup by Sebastien
2008-02-05 22:33:35 +00:00
Stanislav Shwartsman
033150c7e6
According to AMD docs opcodes 0f 19...0f 1f are multibyte NOP
2007-11-17 16:19:14 +00:00
Stanislav Shwartsman
de72d9141f
Disasm updates (bugfixes) + disasm of all SSE4_2 instructions
2007-10-01 19:57:46 +00:00
Stanislav Shwartsman
0dc4badfbb
Added SSE4A and SSE4_2 to disassembler
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Implemented POPCNT instruction
2007-09-19 19:38:10 +00:00
Stanislav Shwartsman
b64fc08c54
implement prefetch hint opcodes
2007-08-23 16:47:51 +00:00
Stanislav Shwartsman
5189cfbf10
SSE4 support
2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
2d47748f52
Added instruction set field for opcodes table + few bugfixes
2007-04-02 10:47:48 +00:00
Stanislav Shwartsman
4bb19c2dc3
Fixed deciding and disasm of CALL in 64-bit mode (no 16-bit calls allowed)
2007-03-28 21:20:09 +00:00
Stanislav Shwartsman
4f166369a6
Fixes for VMX disasm
2007-03-23 22:07:49 +00:00
Stanislav Shwartsman
ef542b3790
Learn to decode and disassemble VMX opcodes
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No fetchdecode support but everything is ready
2007-03-23 14:35:50 +00:00
Stanislav Shwartsman
f39abc9b65
Fix for bug
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[ 1513544 ] disasm of 0xec (in AL,DX) returns ilen of 2 instead of 1
2006-06-27 19:26:53 +00:00
Stanislav Shwartsman
caee480547
Fixed DR registers disasm
2006-06-26 21:06:26 +00:00
Stanislav Shwartsman
4d1a609c8c
BSWAP 16-bit mode not exists, correctly disasm this case
2006-05-07 19:12:56 +00:00
Stanislav Shwartsman
c7773adac4
Norhing changed in funtionality, just make the file significantly smaler by removing extra spaces
2006-04-05 20:54:30 +00:00
Stanislav Shwartsman
f8c3968d42
Changes list made after CVS service crash:
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- Fixed critical bug in CPU code added with one of the prev commits
- Disasm support for SSE4
- Rename PNI->SSE3 everywhere in the code
- Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
- Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
- Fixed ENTER and LEAVE instructions in x86-64 mode
- Added ability to turn ON instruction trace, only GUI support is missed.
Instruction trace could be enabled if Bochs was compiled with disasm
- More changes Bit32u -> bx_phy_address
- Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
- Small code cleanup
- Update CHANGES and user docs
2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
6b2ab6aa92
Fixed movhps/movlps instructions disasm
2006-02-17 17:13:58 +00:00
Stanislav Shwartsman
2dc81b172a
Fixed several disasm bugs
2006-02-17 13:33:05 +00:00
Stanislav Shwartsman
24d4de03a1
- Fixed bug with missed ES segment override prefix
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- Correctly disassemble x86-64 opcodes
Ia_cvttsd2si_Gq_Wsd
Ia_cvttss2si_Gq_Wss
Ia_cvtsd2si_Gq_Wsd
Ia_cvtss2si_Gq_Wss
Ia_movq_Pq_Eq
Ia_movq_Vdq_Eq
Ia_movq_Eq_Pq
Ia_movq_Eq_Vq
- Correctly disassemble Intel SSE3 opcodes (not supported by Bochs)
Ia_monitor
Ia_mwait
2006-01-31 17:42:31 +00:00
Stanislav Shwartsman
934f552ea3
Fix disassembly
2006-01-30 17:39:17 +00:00
Stanislav Shwartsman
276c006129
Merge new disasm module with x96-64 support
2005-12-23 14:15:13 +00:00
