Commit Graph

11 Commits

Author SHA1 Message Date
Stanislav Shwartsman
690bae9a12 add fields and bits for newly announced x86 features and vmx state 2024-04-26 22:13:08 +03:00
Stanislav Shwartsman
38b1bbf4ff Implemented VMX 'Shadow Stack Prematurely Busy' and secondary VMEXIT controls 2024-01-27 13:34:51 +02:00
Stanislav Shwartsman
54831068df
implement RDMSRLIST/WRMSRLIST instructions (+related VMX extensions) (#176) 2023-12-16 21:59:34 +02:00
Stanislav Shwartsman
2e89b9bcba
implemented WAITPKG instruction set (#150)
still missing : UMWAIT/TPAUSE should set CF flag if it was using OS
deadline and woken up after deadline (i.e. not from monitored store)
also not clear in the spec: should UWAITX/TPAUSE always wait until
deadline due to 'while(tsc<deadline)' statement ?
+include small fixes for AMD's MONITORX/MWAITX
2023-12-01 18:00:03 +02:00
Stanislav Shwartsman
280303d76c
initial code for UINTR implementation (#138)
First step into implementing UINTR - User Level Interrupts ISA extension
To be continued

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Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
2023-11-25 16:43:47 +02:00
Shwartsman
4d08659621 Implement 'Tertiary VMEXEC Controls' for VMX
Currently none of the controls were not enabled, all clear but infra is here
2023-11-23 19:38:59 +02:00
Stanislav Shwartsman
1e4f1624c8 remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
36991e9f59 fixed typo in comment 2019-11-26 17:39:09 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00