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8 Commits

Author SHA1 Message Date
Stanislav Shwartsman
4d1a609c8c BSWAP 16-bit mode not exists, correctly disasm this case 2006-05-07 19:12:56 +00:00
Stanislav Shwartsman
c7773adac4 Norhing changed in funtionality, just make the file significantly smaler by removing extra spaces 2006-04-05 20:54:30 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash: 
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
 2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
6b2ab6aa92 Fixed movhps/movlps instructions disasm 2006-02-17 17:13:58 +00:00
Stanislav Shwartsman
2dc81b172a Fixed several disasm bugs 2006-02-17 13:33:05 +00:00
Stanislav Shwartsman
24d4de03a1 - Fixed bug with missed ES segment override prefix 
- Correctly disassemble x86-64 opcodes

	Ia_cvttsd2si_Gq_Wsd
	Ia_cvttss2si_Gq_Wss
	Ia_cvtsd2si_Gq_Wsd
	Ia_cvtss2si_Gq_Wss
	Ia_movq_Pq_Eq
	Ia_movq_Vdq_Eq
	Ia_movq_Eq_Pq
	Ia_movq_Eq_Vq

- Correctly disassemble Intel SSE3 opcodes (not supported by Bochs)
	Ia_monitor
	Ia_mwait
 2006-01-31 17:42:31 +00:00
Stanislav Shwartsman
934f552ea3 Fix disassembly 2006-01-30 17:39:17 +00:00
Stanislav Shwartsman
276c006129 Merge new disasm module with x96-64 support 2005-12-23 14:15:13 +00:00