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66 Commits

Author SHA1 Message Date
Stanislav Shwartsman
fd15b61d94 keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM 2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
596b3b6eb8 reduce CPU dependencies from fetchdecode module 2017-11-25 20:20:34 +00:00
Stanislav Shwartsman
1e46de78ad add proper alignment of XMM/YMM/ZMM registers within CPU class 2014-06-25 19:12:14 +00:00
Stanislav Shwartsman
1e7b6ff2cd check if XMM reg is clear using dedicated function 2014-03-17 20:50:59 +00:00
Stanislav Shwartsman
b510cf794b complete compressed displ feature support, bugfixes in AVX-512 code 2014-02-11 16:10:31 +00:00
Stanislav Shwartsman
37330682ad remove code duplication, prepare for 512-bit evrsion of cvtps2ph 2014-02-08 19:18:17 +00:00
Stanislav Shwartsman
5cdcd7bef7 Implemented AVX-512 VPMOV* down-conversion stores 2014-01-12 13:08:16 +00:00
Stanislav Shwartsman
af29c8bd60 infrastructure change for avx-512: before going to more new instructions modelling 2014-01-10 19:40:38 +00:00
Stanislav Shwartsman
734d1c7af8 implemented VFIXUPIMM AVX-512 opcodes 2013-12-17 16:44:46 +00:00
Stanislav Shwartsman
cbcf30e911 implement EVEX SAE (suppress all exceptions) contol, implement AVX512 INSTERT/EXTRACTPS opcodes 2013-12-14 12:45:06 +00:00
Stanislav Shwartsman
d681bd868f fixed typo bug in xmm accessor definition 2013-12-07 20:48:41 +00:00
Stanislav Shwartsman
8c3d0aed7a added #UD condition for wrong EVEX.LL setting 2013-12-05 20:40:53 +00:00
Stanislav Shwartsman
ca2793ac76 Debugger: fixed param tree access to 64-bit variables (need to use get64() instead of get()) 
Debugger: if AVX-512 if not supported by current configuration do not print high256 of vector registers and zmm15..zmm31 in AVX command
Implement VBROADCASTF64x4, VBROADCASTF32x4, VBROADCASTFI64x4, VBROADCASTI32x4 AVX-512 instructions
Fetchdecode optimizations and bugfixes
 2013-12-05 19:17:16 +00:00
Stanislav Shwartsman
6d9b16e0f7 Implemented VCMPPS/PD/SS/SD AVX512 instructions 
Implemented AVX512 shift/rotate instructions
 2013-12-03 15:44:23 +00:00
Stanislav Shwartsman
11f082af82 Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions 
Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions
Fix vector length values for AVX-512 (512-bit vector should have length 4)
support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions
move AVX512 load/store and register move operations into dedicated file avx512_move.cc
 2013-11-29 20:22:31 +00:00
Stanislav Shwartsman
4680c22d0e implemented avx-512 masked register moves 2013-11-28 20:58:31 +00:00
Stanislav Shwartsman
1beeb33b51 implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables 2013-11-25 20:42:24 +00:00
Stanislav Shwartsman
f791802286 infrastructure change for several AVX handlers to support any VL and only 128/256 2013-09-21 20:40:57 +00:00
Stanislav Shwartsman
cd55ace8c8 fixed compilation err, rename opcode and handler functions for PUSHA/POPA instructions 2013-09-21 10:03:49 +00:00
Stanislav Shwartsman
3803ac7fbe fixed evex override mscsr controls 2013-09-19 21:38:25 +00:00
Stanislav Shwartsman
d169860f6c added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h 2013-09-17 20:49:26 +00:00
Stanislav Shwartsman
aa25c1db6a name convention change - search and replace 2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
1cebe5f83d rellback part of commit with xmm register access interface changes - doesn't work for big endian hosts 2013-09-16 19:10:42 +00:00
Stanislav Shwartsman
0cb0acc30f added evex decode tables - next step to populate them :) 2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
5d61c19b0b evex support - step2 2013-08-27 20:47:24 +00:00
Stanislav Shwartsman
2dbe81db51 first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel 2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions. 
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
 2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
9fbf7d2f15 small cleanups 2011-05-04 05:53:17 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
f705cbbc63 rename functions 2010-12-25 19:34:43 +00:00
Stanislav Shwartsman
c005444d5b split more SSE opcodes 2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
040a8e1a3a split bunch of SSE opcodes 2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
709059ddcc integrate misaligned SSE into code 2010-12-22 21:24:19 +00:00
Stanislav Shwartsman
9ed116ada7 avoid similar issues (like it was in mmx.cc) in future 2010-09-26 20:35:24 +00:00
Stanislav Shwartsman
033a20b3b2 allow to configure CPU features at runtime - implemened on example of SSE/AES/MOVBE/POPCNT 2010-02-25 22:04:31 +00:00
Stanislav Shwartsman
7254ea36a1 copyright fixes + small optimization 2009-10-14 20:45:29 +00:00
Stanislav Shwartsman
e15bfef9f7 remove --enable-daz option, it will be turned on by default iff SSE2 is supported (like in real hardware) 2009-07-08 14:02:42 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
420f30816d inline integer saturation code - speedup for MMX/SSE integer 2008-04-06 13:56:22 +00:00
Stanislav Shwartsman
b929a2b2b8 Fixed minor issues - compilation and not only 2008-02-13 17:06:44 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
58a2595bca Misaligned SSE support 2007-07-15 19:03:39 +00:00
Stanislav Shwartsman
5189cfbf10 SSE4 support 2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
26f08fdb2c Change my e-mail to #SF one 2007-03-23 21:27:13 +00:00
Stanislav Shwartsman
a010cfb8ca Fix amount of XMM registers in non-x86-64 mode 2006-05-22 21:17:27 +00:00
Volker Ruppert
5e75dc3a10 - some more warnings in MSVC fixed 2005-06-06 20:14:50 +00:00
Stanislav Shwartsman
d10731f162 Update my e-mail in source files 
Update committed SF patches in changes
 2005-05-12 18:07:48 +00:00