Stanislav Shwartsman
1bf18b8aae
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
This enable better compiler optimizations and reduce binary size
2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
e15012cfcf
fix code duplication in <limiting max cpuid leaf to 0x02 for winnt> feature
2021-01-02 16:28:51 +00:00
Stanislav Shwartsman
c6050a99d1
implemented AVX encoded VNNI instructions published in recent SDM - not tested yet
2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
a378441254
update CPUID bits and CR bits according to recently published SDM documents by Intel
2020-10-03 07:59:47 +00:00
Stanislav Shwartsman
4023b640d6
Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS)
2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
355c06e396
add defines for CPUID bits recently announced
2020-04-01 06:15:54 +00:00
Stanislav Shwartsman
a70df308fa
add defines for CPUID bits published in latest SDM 071
2019-11-12 18:54:08 +00:00
Stanislav Shwartsman
d766cc8112
implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition
2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
2eb47f866f
added minor clarifications based on most recent AMD SDM published
2019-07-30 18:17:21 +00:00
Stanislav Shwartsman
85780d939a
extract MONITOR/MWAIT stuff to separate trsnlation unit
2019-05-25 18:32:17 +00:00
Stanislav Shwartsman
55d2dc6b0c
add some CPUID and VMCS definitions from latest SDM
2019-05-22 18:22:22 +00:00
Stanislav Shwartsman
9bc7faf493
dump all supported CPU fetures into Bochs log from CPUID object
2019-01-05 20:17:39 +00:00
Stanislav Shwartsman
e387876145
Enable PML VMX feature in Skylake-X
2018-10-26 19:54:22 +00:00
Stanislav Shwartsman
d000e21001
added MOVDIRI opcode implementation
2018-04-06 05:06:36 +00:00
Stanislav Shwartsman
fd15b61d94
keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM
2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
8c9f7f54b6
update CPUID definitions with recently published EAS-33 extensions document
2018-04-04 18:15:44 +00:00
Stanislav Shwartsman
afc2ee6bfd
Implemented SPP: EPT-Based Subpage Protection. Cleaned code duplication between FXSAVE/FXRSTORE and XSAVE/XRSTOR (save/restore of SSE code is the same)
2018-01-27 21:20:33 +00:00
Stanislav Shwartsman
69f27439db
added new cpuid flags mentioned in new Intel SDM future extensions rev030 doc
2017-10-13 20:27:52 +00:00
Stanislav Shwartsman
b2fdbd1274
added Skylake-X model to CPUDB -> with EVEX and AVX512 support
2017-08-09 20:36:17 +00:00
Stanislav Shwartsman
e5c64b3b56
cleanup of warning messages from cpuid code
2017-03-26 20:12:14 +00:00
Stanislav Shwartsman
6edf22e754
finally figured out what TCE means in AMD CPUID - and it has EFER.TCE bit related to it
2017-03-15 22:48:27 +00:00
Stanislav Shwartsman
3a033fa6db
implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen)
2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
402e2cfad0
move cpuid warning messages to base cpuid class - reduce code cleanup
2017-03-13 19:59:48 +00:00
Stanislav Shwartsman
980eaa7937
move cpuid leaf 80000008 to base bx_cpuid_t class to remove code dupolication
2017-03-09 21:25:18 +00:00
Stanislav Shwartsman
9bd99a604f
implemented recently announced AVX-512 extension VPOPCNT
2016-12-17 13:47:45 +00:00
Stanislav Shwartsman
239f793f37
in the latest intel docs PCOMMIT CPUID bit doesn't exists anymore
2016-10-02 11:54:19 +00:00
Stanislav Shwartsman
793ceb0d8c
fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header
2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
adc143684b
implemented Intel architecture extensions published in recently published SDM 058:
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! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction
Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
bcb36e81fa
experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys
2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
88be61c3d9
add new cpuid bit announced in sdm rev057
2015-12-29 20:21:08 +00:00
Stanislav Shwartsman
8d13b61319
implemented TSC Scaling VMX feature according to timestamp-counter for virtualization whitepaper published by Intel
2015-09-30 18:44:01 +00:00
Stanislav Shwartsman
be4b73c6d2
extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class
2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
9315742f3d
cleanups of vmcs mapping related stuff
2015-07-07 21:06:56 +00:00
Stanislav Shwartsman
5fe1423ab6
introducr new class for VMCS mapping so it can be customized per cpuid
2015-07-06 18:46:57 +00:00
Stanislav Shwartsman
bc25883087
add new definitions from most recent AMD Software Developers Manual update. TODO: implement new AMD's MONITORX/MWAITX extensions
2015-06-22 21:46:50 +00:00
Stanislav Shwartsman
2185d21eb7
fixed comments for PML acronym
2015-05-05 19:52:05 +00:00
Stanislav Shwartsman
16ab385e1d
added cpuid/creg bits definition announced in recent 054 update of Intel SDM
2015-05-05 19:28:25 +00:00
Stanislav Shwartsman
080ceb8293
don't crash when running on 386 with no FPU model
2015-03-27 21:39:24 +00:00
Stanislav Shwartsman
901b7be1a8
code reorg
2015-02-12 20:18:35 +00:00
Stanislav Shwartsman
b60d7d3154
Cleanup of CPUDB modules, moved common functionality into bx_cpuid_t base class
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Added Pentium (P54C) AKA Pentium with no MMX to CPUDB
2015-02-11 21:31:17 +00:00
Stanislav Shwartsman
03dab0b0c9
remove debug prints from param tree dump in xml format, small code reorg
2014-11-30 21:26:33 +00:00
Stanislav Shwartsman
987e2ad223
Added definitions from recently published Intel Architecture
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Instruction Set Extensions Programming Reference rev22.
Implemented CLWB instruction
2014-11-01 13:12:24 +00:00
Stanislav Shwartsman
5f4e7f8b49
fixed compilation when APIC if snot enabled
2014-11-01 10:25:42 +00:00
Stanislav Shwartsman
618bc234ab
changes in comments
2014-10-24 11:18:52 +00:00
Stanislav Shwartsman
caab07e580
move common code (extended topology leaf) into base cpuid class to save code duplication
2014-10-15 14:25:08 +00:00
Stanislav Shwartsman
f8267ec3a7
rework in CPUID code (fixed code duplication). Re-enable perfmon reporting in CPUID because Win8/Win10 installation doesn't want to start without perfmon reported. TODO: implement basic perfmon support (at least only fixed counters) because win7-64 doesn't install with perfmon reported but not implemented
2014-10-15 08:04:38 +00:00
Stanislav Shwartsman
e2e6f5a62b
Update CPUID defines after recently published
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Intel Architecture Instruction Set Extensions Programming Reference rev-021
Enable AVX-512 with all implemented extensions in generic CPUID when simd=AVX512 is supplied
implemented AVX512_IFMA532 instructions
implemented AVX512_VBMI instructions
still missing: VPMULTISHIFTQB - VBMI instruction (coming soon)
2014-09-26 12:14:53 +00:00
Stanislav Shwartsman
b6147d9de8
fixed debugger enabled code
2014-08-31 18:48:04 +00:00
Stanislav Shwartsman
9f57e70d5f
Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions
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Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
94864fb9bc
Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20.
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https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf
Most of the instructions are implemented, more on the way.
+ few bugfixes for legacy AVX-512 emulation
AVX-512: Fixed bug in VCMPPS masked instruction implementation with 512-bit data size
AVX-512: Fixed AVX-512 masked convert instructions with non-k0 mask (behaved as non masked versions)
AVX-512: Fixed missed #UD due to invalid EVEX prefix fields for several AVX-512 opcodes (VFIXUPIMMSS/SD, FMA)
2014-07-18 11:14:25 +00:00
