Stanislav Shwartsman
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4d10852c04
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impemented recently published VP2INTERSECTD/Q instructions
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2019-05-25 19:07:09 +00:00 |
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Stanislav Shwartsman
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662b252507
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added missing endif
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2019-04-17 16:04:34 +00:00 |
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Stanislav Shwartsman
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a022d71774
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fixed compilation
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2019-04-14 04:05:04 +00:00 |
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Stanislav Shwartsman
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54bdb24e4b
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remove MOVDIRI opcode extension for now until fugured out how nicely do MOVDIR64B, they better to be both done with same CPUID feature name
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2019-02-22 19:15:53 +00:00 |
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Stanislav Shwartsman
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3e007fbdea
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fixed copy-pasted issue with decoding
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2019-02-17 21:54:38 +00:00 |
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Stanislav Shwartsman
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c3f7a34cf5
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fixed copy-pasted issue with decoding
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2019-02-17 21:41:45 +00:00 |
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Stanislav Shwartsman
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3da93728b3
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split some opcode reference tables in new decoder between x86-64 and 32 for better perf
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2019-02-17 21:22:54 +00:00 |
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Stanislav Shwartsman
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cd79d22113
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fixes for 32-bit mode only compilation
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2019-02-16 19:42:04 +00:00 |
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Stanislav Shwartsman
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4f625b23e0
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enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore
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2019-02-16 15:23:24 +00:00 |
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Stanislav Shwartsman
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61dcc4ace7
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remove unreferenced decode table
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2019-01-29 13:44:39 +00:00 |
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Stanislav Shwartsman
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f8ec18acd5
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fix decode/disasm of AVX512-VBMI2 VPSH*D* opcodes
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2019-01-27 18:52:03 +00:00 |
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Stanislav Shwartsman
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0b18a42e4e
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fixed decoding of AVX-512 opcodes
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2019-01-27 17:35:21 +00:00 |
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Stanislav Shwartsman
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5cb4639891
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fixed decoding of AVX-512 opcodes
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2019-01-27 17:31:28 +00:00 |
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Stanislav Shwartsman
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6dc5cfe80b
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fixed typo in opcode name
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2019-01-24 20:10:46 +00:00 |
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Stanislav Shwartsman
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af75c2a81e
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fixed comment in the opcode table for EVEX
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2019-01-22 18:31:39 +00:00 |
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Stanislav Shwartsman
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9bc7faf493
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dump all supported CPU fetures into Bochs log from CPUID object
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2019-01-05 20:17:39 +00:00 |
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Stanislav Shwartsman
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fcd9ce1634
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fix compilation without x86_64
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2018-04-15 14:22:16 +00:00 |
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Stanislav Shwartsman
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d000e21001
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added MOVDIRI opcode implementation
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2018-04-06 05:06:36 +00:00 |
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Stanislav Shwartsman
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fd15b61d94
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keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM
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2018-04-04 19:31:56 +00:00 |
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Stanislav Shwartsman
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8c9f7f54b6
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update CPUID definitions with recently published EAS-33 extensions document
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2018-04-04 18:15:44 +00:00 |
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Stanislav Shwartsman
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0cd49ddae4
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fixed compilation with EVEX disabled
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2018-03-29 08:50:38 +00:00 |
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Stanislav Shwartsman
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773f1b7e42
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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Stanislav Shwartsman
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769ed3ef88
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fixed MOVBE instruction decoding
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2018-01-23 19:53:34 +00:00 |
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Stanislav Shwartsman
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3c08cfedf2
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fixed buffer overflow when printing instruction disasm for opcode bytes which cannot be decoded
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2017-12-31 21:22:04 +00:00 |
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Stanislav Shwartsman
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6566cab8aa
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fixed new disasm for avx2 opcodes
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2017-12-30 18:45:21 +00:00 |
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Stanislav Shwartsman
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4c03fe3e2c
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fixed disasm of vcvtps2ph/ph2ps opcodes
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2017-12-28 19:59:42 +00:00 |
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Stanislav Shwartsman
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ed8fa8ac61
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fix compilation with no AVX enabled
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2017-12-24 15:38:21 +00:00 |
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Stanislav Shwartsman
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ca034f0642
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fixed disasm of sse insertps instruction
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2017-12-21 18:18:10 +00:00 |
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Stanislav Shwartsman
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59c542fb06
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fix disasm of FISTTP opcodes
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2017-12-19 20:36:55 +00:00 |
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Stanislav Shwartsman
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4337a062e2
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disasm memsize for gather opcodes
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2017-12-19 19:51:55 +00:00 |
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Stanislav Shwartsman
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15187110ef
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implement disasm of implicit memory reference for maskmovdqu/maskmovq opcodes. fix vmaskmovdqu disasm for legacy disasm as well
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2017-12-19 19:45:30 +00:00 |
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Stanislav Shwartsman
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e086f7ba19
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split INSERTPS opcode to reg and mem forms
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2017-12-19 19:25:40 +00:00 |
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Stanislav Shwartsman
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ce3eafa535
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disasm fix
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2017-12-17 18:47:21 +00:00 |
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Stanislav Shwartsman
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79ec183ff6
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fixup for MMX opcodes disasm
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2017-12-17 17:21:02 +00:00 |
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Stanislav Shwartsman
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5dc5e01a12
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disasm fixes and reorg of pinsr* opcodes
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2017-12-16 18:34:20 +00:00 |
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Stanislav Shwartsman
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6a4e8ff2f1
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fixed typo in prev commit
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2017-12-13 21:08:10 +00:00 |
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Stanislav Shwartsman
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f362f34ed6
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correctly decode PINSRQ instruction
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2017-12-13 20:59:41 +00:00 |
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Stanislav Shwartsman
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50a799ea11
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split handlers for PINSRD/Q opcodes. fix disasm for MULX instruction
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2017-12-13 20:18:59 +00:00 |
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Stanislav Shwartsman
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07bff3be43
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fixed decoding of VPINSRB/W/D/Q and VINSERTPS with EVEX prefix
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2017-12-13 20:02:12 +00:00 |
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Stanislav Shwartsman
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8a311515dd
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correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only
fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
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2017-12-13 19:51:25 +00:00 |
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Stanislav Shwartsman
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2f3c9d3c8c
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correct disasm for movsxd opcode
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2017-12-13 18:44:13 +00:00 |
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Stanislav Shwartsman
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c1dc514c2a
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clarify disasm of movlhps/movhlps opcodes
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2017-12-12 08:55:09 +00:00 |
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Stanislav Shwartsman
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fd953421f4
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new disasm: add correct memaccess size for FLDCW
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2017-12-11 19:58:09 +00:00 |
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Stanislav Shwartsman
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a84d9cf1c7
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disasm: fix crc32 operand description
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2017-12-11 19:45:50 +00:00 |
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Stanislav Shwartsman
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a028ef7c9c
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bugfix for decoder with EVEX enabled
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2017-12-11 19:29:11 +00:00 |
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Stanislav Shwartsman
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e46f37b40e
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fixed disasm of memsize for sse legacy instructions
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2017-12-11 18:33:33 +00:00 |
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Stanislav Shwartsman
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404a5f2c53
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bugfix for previous commit
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2017-12-11 16:41:48 +00:00 |
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Stanislav Shwartsman
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b03f78d652
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updates for bochs decoder and decoder based disasm
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2017-12-11 15:45:43 +00:00 |
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Stanislav Shwartsman
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c80e587ded
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properly handle kmask registers in modrm form
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2017-12-05 19:33:23 +00:00 |
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Stanislav Shwartsman
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8f15cfb514
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fixed link err with debugger enabled
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2017-12-05 19:23:41 +00:00 |
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Stanislav Shwartsman
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31ea453921
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fixed bogus assert
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2017-12-02 16:40:03 +00:00 |
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Stanislav Shwartsman
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eaa05c32e8
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link without LOGIO for standalone decoder mode
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2017-12-01 21:27:30 +00:00 |
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Stanislav Shwartsman
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60591800f1
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handle lock mov cr0 amd feature out decoder critical path
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2017-12-01 21:18:16 +00:00 |
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Stanislav Shwartsman
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01067cb4b9
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another compilation fix for new disasm stand-alone module
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2017-11-29 19:24:00 +00:00 |
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Stanislav Shwartsman
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a7e58973ce
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fixed typo
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2017-11-27 20:26:54 +00:00 |
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Stanislav Shwartsman
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c8d9aeb377
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mark blocks of code which not supposed to be compiled for stand-alone bochs cpu decoder
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2017-11-27 20:25:04 +00:00 |
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Stanislav Shwartsman
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cef6c7fb98
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fix for new disasm
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2017-11-26 19:38:58 +00:00 |
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Stanislav Shwartsman
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596b3b6eb8
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reduce CPU dependencies from fetchdecode module
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2017-11-25 20:20:34 +00:00 |
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Stanislav Shwartsman
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180386cd74
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VMOVSS/VMOVSD are VEX.VL ignore form and not VEX.L0
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2017-11-11 11:58:07 +00:00 |
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Stanislav Shwartsman
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f89b8a2742
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fixed opcode of ADOX instr
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2017-11-11 10:42:21 +00:00 |
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Stanislav Shwartsman
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8261a91ce9
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implemented GFNI instructions
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2017-10-21 19:57:12 +00:00 |
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Stanislav Shwartsman
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b7f62a291c
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fixed compressed displ form for more avx512 instructions
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2017-10-20 19:41:32 +00:00 |
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Stanislav Shwartsman
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da8d6e793f
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fixed compilation issues
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2017-10-20 19:24:10 +00:00 |
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Stanislav Shwartsman
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bca076889b
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decode all the vbmi2 opcodes, fix vpcompress/vpexpand instruction handler names (affects disasm)
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2017-10-20 18:50:10 +00:00 |
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Stanislav Shwartsman
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77a62a4dcd
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implemented (experimental, still untested) AVX512 VBMI2 extensions
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2017-10-20 18:38:15 +00:00 |
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Stanislav Shwartsman
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5439647254
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small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in
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2017-10-19 21:27:25 +00:00 |
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Stanislav Shwartsman
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ba1e5bbffa
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fixed accidentially broken XMM versions of AES instrructions
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2017-10-19 20:25:05 +00:00 |
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Stanislav Shwartsman
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15ba88c195
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implemented VAES/VPCLMULDQ instructions - VEX/EVEX extensions of AES/PCLMULQDQ
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2017-10-19 19:12:55 +00:00 |
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Stanislav Shwartsman
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6daa1ba9ba
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fixed compilation issue with EVEX enabled
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2017-10-15 20:40:56 +00:00 |
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Stanislav Shwartsman
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944f37b1f2
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implemented AVX-512 BITALG instructions/bugfix for VPOPCNT instructions
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2017-10-15 20:33:19 +00:00 |
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Stanislav Shwartsman
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0d190eec8e
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implemented AVX-512 VNNI instructions
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2017-10-15 19:17:07 +00:00 |
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Stanislav Shwartsman
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54e969b749
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disasm update
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2017-06-05 21:05:47 +00:00 |
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Stanislav Shwartsman
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20e9e33662
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internal disasm updates
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2017-06-05 20:49:04 +00:00 |
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Stanislav Shwartsman
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3f4f18de7a
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internal disasm updates
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2017-06-05 20:28:33 +00:00 |
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Stanislav Shwartsman
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46ef85ce0f
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avoid using magic constants for disasm source metadata
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2017-06-05 19:55:40 +00:00 |
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Stanislav Shwartsman
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bb43ac527b
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fixed decoder issue when decoding opcode 8f (aka xop prefix) as well
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2017-05-27 10:32:44 +00:00 |
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Stanislav Shwartsman
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54c109ceb4
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VEX and EVEX opcodes should be considered as 2-byte opcode, always attempt to fetch 2nd byte even if #UD is already detected
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2017-05-26 11:46:02 +00:00 |
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Stanislav Shwartsman
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af76e0c412
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fixes for debugger and disasm
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2017-05-10 18:31:59 +00:00 |
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Stanislav Shwartsman
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1ca366609f
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add memsize for non-evex memory refrences in disasm
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2017-05-09 19:49:27 +00:00 |
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Stanislav Shwartsman
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f8abddafcf
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bugfix in disasm
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2017-05-09 19:34:03 +00:00 |
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Stanislav Shwartsman
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1d48973c80
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updates in fetchdecode.h to help automatic disasm to determined memaccess size
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2017-05-09 12:06:02 +00:00 |
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Stanislav Shwartsman
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1abfcd39ff
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implement FOPCODE and FDP deprecation CPU features
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2017-05-05 20:56:13 +00:00 |
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Stanislav Shwartsman
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862e817884
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fixed typo caused compilation err
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2017-03-28 19:13:20 +00:00 |
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Stanislav Shwartsman
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b7b0165d3c
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new naming convention for UD opcodes
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2017-03-28 19:00:00 +00:00 |
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Stanislav Shwartsman
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2b79061127
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Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model
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2017-03-26 19:14:15 +00:00 |
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Stanislav Shwartsman
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411ea954b4
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implemented CLZERO instruction from AMD Ryzen CPU
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2017-03-25 20:12:31 +00:00 |
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Volker Ruppert
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9bef555f3e
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Updated build test script and fixed compilation without FPU.
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2017-03-19 09:50:16 +00:00 |
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Stanislav Shwartsman
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be4c6c7ae5
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SMAP opcodes are No-SSE-Prefix
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2017-03-16 16:20:58 +00:00 |
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Stanislav Shwartsman
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172b0106ac
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imvent a bochs feature for AMD TCE and enable EFER.TCE bit
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2017-03-15 22:52:08 +00:00 |
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Stanislav Shwartsman
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3a033fa6db
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implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen)
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2017-03-15 21:44:15 +00:00 |
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Stanislav Shwartsman
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8664f8f21e
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add vex.w into bxInstruction to be used in disasm
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2017-01-28 19:25:30 +00:00 |
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Stanislav Shwartsman
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49c537521a
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simplify disasm code by splitting it into functions
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2017-01-22 19:53:42 +00:00 |
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Stanislav Shwartsman
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af1d83f35d
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update (c)
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2017-01-11 20:54:09 +00:00 |
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Stanislav Shwartsman
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521d2d10c4
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correctly fixed x32 emu compilation err + bugfix for AVX decoder
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2017-01-11 20:51:58 +00:00 |
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Stanislav Shwartsman
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72e5213ff4
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compilation fix and code simplifcation
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2017-01-11 19:12:06 +00:00 |
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Stanislav Shwartsman
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90c4cb31c5
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add SVN header to newly added files
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2017-01-10 20:16:24 +00:00 |
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Stanislav Shwartsman
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10eb193e01
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step 1 of rewrite Bochs decoder: legacy decoder tables done. TODO: avx/evex decoder tables, merge decoder and disasm together
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2017-01-10 20:15:17 +00:00 |
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Stanislav Shwartsman
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9bd99a604f
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implemented recently announced AVX-512 extension VPOPCNT
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2016-12-17 13:47:45 +00:00 |
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Stanislav Shwartsman
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e613e9ff86
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fixed compilation err when no AVX is enabled
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2016-12-12 06:18:57 +00:00 |
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Stanislav Shwartsman
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46b4a76cd3
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fetchdecode rework step 0.1, no impact on correctness, small speedup
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2016-12-09 12:34:37 +00:00 |
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