Commit Graph

10 Commits

Author SHA1 Message Date
Stanislav Shwartsman
9f82d7d3e6 Removed already committed patch.highmem
Applied FPU 64but addressing patch
I am starting to work on FPU code so I need the patch committed,
it looks ok and nobody still not complained ;)
2003-07-25 08:59:46 +00:00
Stanislav Shwartsman
aa9152129c Changes in i387 register file definition. Define common FPU/MMX register file. 2003-04-12 21:02:08 +00:00
Christophe Bothamy
e94c6c7d5a - fix [ 648579 ] Mac OSX >>PANIC<< FPU_printall
. correct the signbyte macro for big endian systems
  . group all the endian specific stuff of fpû_emu.h in one place
2002-12-11 12:54:19 +00:00
Christophe Bothamy
7dc434d872 - fix MAKE_REG definition on big endian systems, according to fpu__reg structure.
This hopefully fixes [ 648579 ] Mac OSX >>PANIC<< FPU_printall,
  I will need to check on a real big endian system.
2002-12-10 22:40:16 +00:00
Stanislav Shwartsman
3012e7c361 Fixed representation and aligment of FPU/MMX register(s).
Description/justification:

Endian  Host byte order         Guest (x86) byte order
======================================================
Little  FFFFFFFFEEAAAAAA        FFFFFFFFEEAAAAAA
Big     AAAAAAEEFFFFFFFF	FFFFFFFFEEAAAAAA

F - fraction/mmx
E - exponent
A - aligment
2002-11-30 17:15:59 +00:00
Bryce Denney
16ee3abe6b - add ID line for bochs 2001-10-06 03:53:46 +00:00
Bryce Denney
e61d00351f - merged BRANCH-smp-bochs into main branch. For details see comments
in BRANCH-smp-bochs revisions.
- The general task was to make multiple CPU's which communicate
  through their APICs.  So instead of BX_CPU and BX_MEM, we now have
  BX_CPU(x) and BX_MEM(y).  For an SMP simulation you have several
  processors in a shared memory space, so there might be processors
  BX_CPU(0..3) but only one memory space BX_MEM(0).  For cosimulation,
  you could have BX_CPU(0) with BX_MEM(0), then BX_CPU(1) with
  BX_MEM(1).  WARNING: Cosimulation is almost certainly broken by the
  SMP changes.
- to simulate multiple CPUs, you have to give each CPU time to execute
  in turn.  This is currently implemented using debugger guards.  The
  cpu loop steps one CPU for a few instructions, then steps the
  next CPU for a few instructions, etc.
- there is some limited support in the debugger for two CPUs, for
  example printing information from each CPU when single stepping.
2001-05-23 08:16:07 +00:00
Bryce Denney
4e04f4cb58 - change all inline declarations to one of two macros: BX_C_INLINE or
BX_CPP_INLINE.  Then in config.h.in you can define these two as you
  wish.
2001-04-10 02:10:09 +00:00
Bryce Denney
f850a6df1f These changes are from "portable1" patch.
- put /*comments symbols*/ around any chars after #endif.  Other compilers
  do not get it.
- fix cases in which a pointer is cast to a 32-bit int, then back to a
  pointer.  This breaks on a machine with 64-bit pointers.  Examples:
  FPU_sub arg 2 and FPU_div arg 2.  The int->ptr->int conversions are
  now done more safely by macros REGNO2PTR and PTR2INT.
- use GCC_ATTRIBUTE macro instead of __attribute__.  For compilers that
  do not support __attribute__, the macro can be defined to be nothing.
- in fpu_entry.c, arg1 of FPU_load_int32 is (s32*), but the calls to
  it cast their data to (u32*).
- if compiler does NOT inline functions in poly.h, the "extern inline"
  setting caused duplicate symbols to be created.  Changed them to
  "static inline" so that the mul_32_32 from different .c files do not
  conflict.
- implemented setcc so that it doesn't use curly brackets inside parens
- comment out sigcontext structure definition, which conflicts with
  non-linux or non-intel operating systems.  It's not used by bochs anyway.
2001-04-10 01:43:09 +00:00
cvs
beff63eb32 - entered original Bochs snapshot bochs-2000_0325a.tar.gz from
ftp.bochs.com
2001-04-10 01:04:59 +00:00