Stanislav Shwartsman
e086f7ba19
split INSERTPS opcode to reg and mem forms
2017-12-19 19:25:40 +00:00
Stanislav Shwartsman
5dc5e01a12
disasm fixes and reorg of pinsr* opcodes
2017-12-16 18:34:20 +00:00
Stanislav Shwartsman
50a799ea11
split handlers for PINSRD/Q opcodes. fix disasm for MULX instruction
2017-12-13 20:18:59 +00:00
Stanislav Shwartsman
8a311515dd
correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only
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fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
2017-12-13 19:51:25 +00:00
Stanislav Shwartsman
596b3b6eb8
reduce CPU dependencies from fetchdecode module
2017-11-25 20:20:34 +00:00
Stanislav Shwartsman
8261a91ce9
implemented GFNI instructions
2017-10-21 19:57:12 +00:00
Stanislav Shwartsman
77a62a4dcd
implemented (experimental, still untested) AVX512 VBMI2 extensions
2017-10-20 18:38:15 +00:00
Stanislav Shwartsman
ba1e5bbffa
fixed accidentially broken XMM versions of AES instrructions
2017-10-19 20:25:05 +00:00
Stanislav Shwartsman
15ba88c195
implemented VAES/VPCLMULDQ instructions - VEX/EVEX extensions of AES/PCLMULQDQ
2017-10-19 19:12:55 +00:00
Stanislav Shwartsman
ac442009aa
lazy flags code small refactoring
2017-10-15 22:01:32 +00:00
Stanislav Shwartsman
944f37b1f2
implemented AVX-512 BITALG instructions/bugfix for VPOPCNT instructions
2017-10-15 20:33:19 +00:00
Stanislav Shwartsman
0d190eec8e
implemented AVX-512 VNNI instructions
2017-10-15 19:17:07 +00:00
Stanislav Shwartsman
1abfcd39ff
implement FOPCODE and FDP deprecation CPU features
2017-05-05 20:56:13 +00:00
Stanislav Shwartsman
097310cd00
fixed integer overflow while computing shift flags, avoid using bx_bool while working with flags for more robust code
2017-03-30 21:53:39 +00:00
Stanislav Shwartsman
a673612784
fixed permission checks performed by CLFLUSH/CLFLUSHOPT/MONITOR* instructions
2017-03-28 18:52:53 +00:00
Stanislav Shwartsman
2b79061127
Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model
2017-03-26 19:14:15 +00:00
Stanislav Shwartsman
411ea954b4
implemented CLZERO instruction from AMD Ryzen CPU
2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
15d9b068a3
fix msvc warnings
2017-03-17 17:35:15 +00:00
Stanislav Shwartsman
3a033fa6db
implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen)
2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
9bd99a604f
implemented recently announced AVX-512 extension VPOPCNT
2016-12-17 13:47:45 +00:00
Stanislav Shwartsman
7a34f00f99
extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all
2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
8824539630
fix code duplication in segload instr emulation
2016-06-01 20:11:54 +00:00
Stanislav Shwartsman
e24c7e403a
take a funtion from BX_CPU_C:: into fetchdecode.cc standalone function
2016-04-30 19:13:15 +00:00
Stanislav Shwartsman
793ceb0d8c
fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header
2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
cc49b504b3
fix small issue on the way to Bochs decoder separation into stand-alone module
2016-04-26 12:46:44 +00:00
Stanislav Shwartsman
adc143684b
implemented Intel architecture extensions published in recently published SDM 058:
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! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction
Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
e4832af5ab
clean pkeys when not enabled to avoid side-effects
2016-03-19 21:15:56 +00:00
Stanislav Shwartsman
bcb36e81fa
experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys
2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
9308ad31c6
remove unused param from serveIcacheMiss
2016-02-22 19:57:24 +00:00
Stanislav Shwartsman
9557cafcef
revertng commit #12854 because it broke MT simulation with debugger enabled. Until investigted.
2015-12-20 22:44:54 +00:00
Stanislav Shwartsman
a8a325f2f5
#define to enum or inline function convertion
2015-10-09 19:33:36 +00:00
Stanislav Shwartsman
9f77a6c3b0
full debugger support together with handler-chaining speedups optimization enabled (experimental)
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should speedup emulation with debugger enabled
2015-10-09 05:28:47 +00:00
Stanislav Shwartsman
be4b73c6d2
extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class
2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
f6af0443bb
small optimization and elimination of several defines from cpu.h - replace by inline functions and const variables
2015-07-13 20:24:14 +00:00
Stanislav Shwartsman
5fe1423ab6
introducr new class for VMCS mapping so it can be customized per cpuid
2015-07-06 18:46:57 +00:00
Stanislav Shwartsman
c43ea147bf
~1% emulation speedup by skipping pageWriteStamp check for stack writes.
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For now the optimization is supported only when no SMP is compiled in because it doesn't handle cross-modifying code.
The current stack page will cache also current pageWriteStamp for that page and could skip pageWriteStamp access if possible.
Any code fetch access missing trace cache will invalidate current stack page.
Code fetch accesses from another SMP threads should do the same to support SMP.
Next step:
- support SMP
- support pageWriteStamp access skipping for all other memory writes from all segments
2015-05-23 19:34:59 +00:00
Stanislav Shwartsman
b468316250
re-style old resolve macros after resolve function inlining
2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
f0d7379908
remove BxResolveModrm member in BxInstruction_c class and inline resolve functions into instruction handlers instead. helps to remove indirect branch mispredictions (suggested by Vtune). measured speedup on Win7-64 boot is 5%, on other guests it might vary between 1% and 5%
2015-05-16 20:29:49 +00:00
Stanislav Shwartsman
9f18573740
Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only)
2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
b9b45f0d0d
convert some defines to typed consts
2015-05-10 19:54:57 +00:00
Stanislav Shwartsman
0d79c5f986
Implemented Page Modification Logging VMX feature
2015-05-06 19:55:44 +00:00
Stanislav Shwartsman
c360ddf60c
correctly report memory type for EPT page table accesses
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TODO: support memory type for guest physical access under EPT
TODO: support memory type for SVM nested paging
TODO: check what happens when PAT is not enabled in CPU configuration
2015-03-23 20:27:36 +00:00
Stanislav Shwartsman
a55c5e4eb8
correctly report memory type for page table accesses in x86 mode (not in EPT or SVM nested paging yet)
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TODO: support memory type with EPT / nested paging
TODO: check what happens when PAT is not enabled in CPU configuration
2015-03-21 20:08:58 +00:00
Stanislav Shwartsman
e79185b0a0
refactor memtype methods
2015-03-02 20:51:59 +00:00
Stanislav Shwartsman
25b02dac4b
code reorg before PAT memory type support
2015-02-28 14:01:11 +00:00
Stanislav Shwartsman
1e1c893041
introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it
2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
2bad0d0d12
fixed link error with debugger enabled, small speed optimization
2015-02-23 19:55:55 +00:00
Stanislav Shwartsman
0917d12e8b
memory type report for physical accesses and RMW acccesses. todo: consider also pat
2015-02-22 21:26:26 +00:00
Stanislav Shwartsman
7a3e340e6d
implement memory type calculation by mtrr. todo: memory type from page tables
2015-02-20 21:50:59 +00:00
Stanislav Shwartsman
e16c6eb30c
preparations and interface definition for memory type support
2015-02-19 20:23:08 +00:00