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417 Commits

Author SHA1 Message Date
Stanislav Shwartsman
9f57e70d5f Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions 
Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
 2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
94864fb9bc Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20. 
https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf

Most of the instructions are implemented, more on the way.

+ few bugfixes for legacy AVX-512 emulation

AVX-512: Fixed bug in VCMPPS masked instruction implementation with 512-bit data size
AVX-512: Fixed AVX-512 masked convert instructions with non-k0 mask (behaved as non masked versions)
AVX-512: Fixed missed #UD due to invalid EVEX prefix fields for several AVX-512 opcodes (VFIXUPIMMSS/SD, FMA)
 2014-07-18 11:14:25 +00:00
Stanislav Shwartsman
0b2364501d fixed compilation err when 3dnow is ON 2014-06-01 10:46:17 +00:00
Stanislav Shwartsman
8fbf673295 fixed compilation errors with FPU off 2014-04-29 18:49:38 +00:00
Stanislav Shwartsman
211208dc30 zero masking is not allowed for all forms of vsib, including gather 2014-03-08 20:27:10 +00:00
Stanislav Shwartsman
069498eef6 zero masking is not allowed for mem destination instructions 2014-03-08 19:49:35 +00:00
Stanislav Shwartsman
b510cf794b complete compressed displ feature support, bugfixes in AVX-512 code 2014-02-11 16:10:31 +00:00
Stanislav Shwartsman
9613e4b402 implementation of AVX-512 compressed displacement feature which is required for AVX-512 emu correctness (first step). todo: fix rest of EVEX opcodes 2014-02-10 21:12:08 +00:00
Stanislav Shwartsman
ba52890538 implemented few more AVX-512 floating point convert instructions 2014-01-18 20:10:05 +00:00
Stanislav Shwartsman
58470763fa implement few more avx-512 opcodes 2013-12-31 23:51:25 +00:00
Stanislav Shwartsman
15756a31cd implemented EVEX MOVD/MOVQ opcodes, fixes in softfloat 2013-12-13 12:05:47 +00:00
Stanislav Shwartsman
9c179bade8 fixed evex.b validation condition 2013-12-10 21:48:17 +00:00
Stanislav Shwartsman
258a60f3fa Implemented AVX512 EXPAND/COMPRESS instructions 
Fixed memory access size for AVX shift instructions with shift count in memory
Do not allow to encode with EVEX.b instructions which do not support implicit broadcast 
softfloat: prepare float32/64 to uint32 conversion functions
 2013-12-10 21:09:46 +00:00
Stanislav Shwartsman
ccb1d86d6e code cleanups 2013-12-09 20:36:24 +00:00
Stanislav Shwartsman
d20c81417c Implemented VSHUFF32x4/64x2, VSHUFI32x4/64x2 AVX512 instructions 
Implemented AVX512 blend instructions
Do not allow setting of EVEX.b in reg form when no floating point exceptions could be generated by instruction
 2013-12-09 19:09:37 +00:00
Stanislav Shwartsman
1e474ede51 fixed corrupted fetchdecode from svn rev12001 2013-12-07 20:30:27 +00:00
Stanislav Shwartsman
8c3d0aed7a added #UD condition for wrong EVEX.LL setting 2013-12-05 20:40:53 +00:00
Stanislav Shwartsman
ca2793ac76 Debugger: fixed param tree access to 64-bit variables (need to use get64() instead of get()) 
Debugger: if AVX-512 if not supported by current configuration do not print high256 of vector registers and zmm15..zmm31 in AVX command
Implement VBROADCASTF64x4, VBROADCASTF32x4, VBROADCASTFI64x4, VBROADCASTI32x4 AVX-512 instructions
Fetchdecode optimizations and bugfixes
 2013-12-05 19:17:16 +00:00
Stanislav Shwartsman
cfc8a0ad38 get rid of BX_MEM_NO_VVV decoding form (by splitting just two opcode groups using Split11B) 2013-12-04 20:15:22 +00:00
Stanislav Shwartsman
0683b00535 implemented more avx-512 opcodes 2013-12-02 19:16:48 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00
Stanislav Shwartsman
f76c85dca9 fixed 512-bit VL encoding in EVEX 2013-11-29 21:05:29 +00:00
Stanislav Shwartsman
11f082af82 Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions 
Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions
Fix vector length values for AVX-512 (512-bit vector should have length 4)
support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions
move AVX512 load/store and register move operations into dedicated file avx512_move.cc
 2013-11-29 20:22:31 +00:00
Stanislav Shwartsman
eb9778220d fixed decoding of 0f3a opcode map 2013-11-20 20:46:03 +00:00
Stanislav Shwartsman
b553591bb4 fixed compilation error under AVX 2013-11-20 17:33:57 +00:00
Stanislav Shwartsman
7f8429c643 fix code duplication in fetchdecode modules 2013-11-20 16:00:24 +00:00
Stanislav Shwartsman
3be7e5884b added lock prefix used info into bx_Instriction_c and use it in disasm 2013-11-08 21:43:21 +00:00
Stanislav Shwartsman
8bcc8cf073 split PREFETCH opcode to Group16 for better disasm of bxInstruction_c 2013-10-15 21:21:28 +00:00
Stanislav Shwartsman
940c2a1c8e fixes for disasm 2013-10-15 17:19:18 +00:00
Stanislav Shwartsman
9fb7384e6b finish sse tables cleanup in disasm and fetchdecode 2013-10-11 20:09:51 +00:00
Stanislav Shwartsman
5fc491e9b6 resolve aliases after actually decoding base instr 2013-10-11 05:58:30 +00:00
Stanislav Shwartsman
46e36b463b size-optimization for SSE opcode tables 2013-10-10 20:21:15 +00:00
Stanislav Shwartsman
0b2e533a55 more avx512 instructions done 2013-10-09 19:45:36 +00:00
Stanislav Shwartsman
70230049fa opmask_ok support in fetchdecode32.cc 2013-10-08 18:40:10 +00:00
Stanislav Shwartsman
09254eb474 avx512 implementation fixes and next steps 2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
5724013e7d updates to AVX512 decoding and CPUID 2013-10-07 20:39:34 +00:00
Stanislav Shwartsman
cb0eee9456 disasm fixes 2013-10-07 19:02:53 +00:00
Stanislav Shwartsman
a392612b03 fixed compilation err in cpu-level=3 config 2013-10-06 18:01:25 +00:00
Stanislav Shwartsman
d4bfbffdbb disasm fixes 2013-10-05 08:34:09 +00:00
Stanislav Shwartsman
ba1249ed15 disasm fixes 2013-10-04 17:26:56 +00:00
Stanislav Shwartsman
85b0402668 fixes for disasm 2013-10-02 19:23:34 +00:00
Stanislav Shwartsman
fd383435f0 - Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon). 
The code already knows to disasm most of the opcodes with their operands.

- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance

- Minimize amount of opcode forms in ia_opcodes.h again.
  For example Udq means the same as Wdq but with no memory form.
 2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
fa06b26c88 Make possible to deliver instruction name for disasm directly from bx_ia_opcode_name (some opcodes were renamed). 
Fixed bug in stack optimization in 64-bit mode (should result in some speedup)
ia_opcode.h - eliminate some OP_M cases when they actually meant "value of specific type in the memory"
example: "MOVBE Md, Gd" actually means "MOVBE Ed, Gd"which just not have reg/reg form.
 2013-09-26 18:54:32 +00:00
Stanislav Shwartsman
839b841c38 added register type to register source information in decoder 2013-09-24 09:50:25 +00:00
Stanislav Shwartsman
ff79cbd596 Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm) 
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.

Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
 2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
404b8b1475 move end of trace indication to separate 'flags' field of bx_ia_opcode. this saves a lot of code duplication and simplifies the decode tables. also on the way found missing SVM opcodes that missed 'end of trace' mark 2013-09-21 18:58:01 +00:00
Stanislav Shwartsman
cd55ace8c8 fixed compilation err, rename opcode and handler functions for PUSHA/POPA instructions 2013-09-21 10:03:49 +00:00
Stanislav Shwartsman
2526282ed9 small additions for avx512 2013-09-20 18:27:33 +00:00
Stanislav Shwartsman
8b3a0acde9 implement first EVEX instructions - VADDPS/PD/SS/SD 2013-09-19 18:31:30 +00:00
Stanislav Shwartsman
8e71a86542 seve vex prefix value to the indication of vex prefix used 2013-09-18 18:01:48 +00:00