Stanislav Shwartsman
0b5f798af1
re-commit changes from SVN rev11026 which were accidentially undo'ed by last Volker's commit
2012-02-12 19:13:57 +00:00
Volker Ruppert
de94b08a1a
- class bx_list_c now contains a chained list of parameters. Removed the now
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obsolete maxsize parameter from all lists.
2012-02-12 18:43:20 +00:00
Stanislav Shwartsman
855d2adece
cleanups in paging code
2012-02-12 16:09:35 +00:00
Stanislav Shwartsman
9bebe91826
eliminate duplicated cpu methods by adding extra param to opcodes with no modrm
2012-02-03 10:24:59 +00:00
Stanislav Shwartsman
14ec87768e
expand FCMOV function to 8 different functions - each one is much simpler to implement and understand
2012-02-01 12:07:53 +00:00
Stanislav Shwartsman
9461797886
added extra param to debugger phy access callback + cleanup in vmexit functions
2012-01-17 21:50:15 +00:00
Stanislav Shwartsman
7d641450ec
remove param from check_entry_PAE function - it is always the same for all calls
2012-01-15 20:25:39 +00:00
Stanislav Shwartsman
4db23355cd
rework in paging code before nested paging implementation for SVM - step 1
2012-01-15 17:54:13 +00:00
Stanislav Shwartsman
f5d55f5eb6
- Implemented Task Switch intercept in SVM, cleanup in task switch handling code
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- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
cb366e00c5
fixed code duplication in exceptions
2012-01-11 06:27:35 +00:00
Stanislav Shwartsman
2900956327
Split back some frequently used arithmetic and logic opcodes (which were done as Load+Op before).
2012-01-09 13:09:59 +00:00
Stanislav Shwartsman
76ee7b499b
svm updates
2012-01-08 14:09:51 +00:00
Stanislav Shwartsman
0e17f8f195
implemented AMD APIC extensions for SVM support
2012-01-04 16:06:37 +00:00
Stanislav Shwartsman
a0b5ff48ec
more SVM fixes
2011-12-31 14:22:51 +00:00
Stanislav Shwartsman
3c0d712146
SVM fixes
2011-12-31 13:58:55 +00:00
Stanislav Shwartsman
0a14f08f16
completing SVM coding, missed - CPUID, extended APIC
2011-12-28 16:12:28 +00:00
Stanislav Shwartsman
2b8371f2b6
implemented SVM_GIF handling
2011-12-27 20:46:15 +00:00
Stanislav Shwartsman
7f5f917a34
more SVM implementation
2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
6ae86a059b
firt cleanup in SVM code. added intercept check for MSR and IO
2011-12-26 19:57:39 +00:00
Stanislav Shwartsman
8b4a2c2034
implemented some more intercepts.
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fixed compilation without SVM
2011-12-26 16:33:13 +00:00
Stanislav Shwartsman
bfcbb81602
SVM:
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- IO intercept is not implemented yet
- MSR intercept is not implemented yet
VMX:
Fixed Bochs PANIC crash when doing I/O access crossing VMX I/O permission bitmaps.
This can happen because access_physical_read and access_physical_write cannot access memory cross 4K boundary.
2011-12-25 22:09:31 +00:00
Stanislav Shwartsman
a44c1b8e1e
SVM and VMX share tsc offset code
2011-12-25 19:53:23 +00:00
Stanislav Shwartsman
75bda1d5cd
implemented SVM emulation support for Bochs (incomplete yet)
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I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.
Also looking for anybody with existing SVM kernels - as simple as possible - for testing.
Status:
- exceptions intercept is not implemented yet
- IO intercept is not implemented yet
- MSR intercept is not implemented yet
- virtual interrupts are not implemented yet
- CPUID is not implemented yet
No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
e7ed8aca5c
move inhibit interrrupts functionality to icount interface
2011-12-21 06:17:45 +00:00
Stanislav Shwartsman
f6203dae7d
instrumentation: added special indication for indirect call/jump
2011-12-18 18:11:56 +00:00
Stanislav Shwartsman
b8f2d91b9a
fixed compilation err
2011-11-28 21:16:40 +00:00
Stanislav Shwartsman
8cb359fab5
fixed flags handling for BMI instructions
2011-11-27 13:23:26 +00:00
Stanislav Shwartsman
100622e958
fix ULL suffix for 64bit int, use BX_CONST64 instead
2011-11-26 19:01:53 +00:00
Stanislav Shwartsman
c74f590077
implemented TSC-Deadline APIC timer mode
2011-11-21 12:51:50 +00:00
Stanislav Shwartsman
9be8552b80
- Implemented VM Functions support and EPTP-Switching VM Functions
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- Added VMEXIT conditions for INVPCID instruction
Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
b1a6b34616
implemented PERMIL2PS/PERMIL2PD XOP instructions
2011-10-20 17:37:57 +00:00
Stanislav Shwartsman
5cc04b9955
Implemented AMDs Buldozer XOP and TBM extensions.
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XOP: few instructions are still missing, coming soon
BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
2580d8c46d
added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions
2011-10-07 14:09:35 +00:00
Stanislav Shwartsman
6751af5d8e
added AVX FMA extensions support. The implementation is based on QEMU patch by Peter Maydell (fixed)
2011-09-29 22:20:56 +00:00
Stanislav Shwartsman
275194fb32
#GP on reading VMX_EPT_VPID_CAP MSR when EPT and VPID disabled
2011-09-26 20:36:26 +00:00
Stanislav Shwartsman
0547c8823e
compilation w/o x86-64
2011-09-26 19:48:58 +00:00
Stanislav Shwartsman
12ad45395b
enable Penryn VMX capabilities with VMX=1, VMX=2 is required for EPT and heavier stuff
2011-09-26 19:36:20 +00:00
Stanislav Shwartsman
0aadf88c07
more polishing for vmx configurability
2011-09-26 18:08:31 +00:00
Stanislav Shwartsman
c28c7f6a06
Supply real VMX capabilities together with the CPU MODEL .bochsrc option.
...
So now the same single option will choose not only the CPUID flags but also VMX capabilities matching real HW machine.
Removed cpuid of core2_extreme_x9770 from the cpudb. I don't remember its VMX capabilities anyway.
There is another Penryn model in the cpudb - core2_penryn_t9600.
2011-09-26 12:31:40 +00:00
Stanislav Shwartsman
b66feecc86
move common instrumentation constants (valid for all stubs) to cpu.h
2011-09-25 17:38:54 +00:00
Stanislav Shwartsman
62d0c8abf7
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
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32-bit CPU using Bochs binary compiled with x86-64 support.
The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
1b9f286945
- New way of CPUs scheduling in SMP mode brings up to 50% speedup to the
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SMP emulation. New implementation uses dynamic CPU quantum value and takes
full advantage of the trace cache. Each emulated processor will execute
the whole trace before switching to the next processor.
* It is also safe to use large (up to 16 instructions) quantum values for
the SMP emulation now and improve performance even further.
The same merge also completely fixes SF bug :
[3312237] stepN command might be not working properly
Handlers chaining speedups are also supported with SMP emulation now.
2011-09-22 19:38:52 +00:00
Stanislav Shwartsman
50207eeb90
- Added support for AMD SSE4A emulation, the instructions can be enabled
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using .bochsrc CPUID option.
2011-09-18 16:18:22 +00:00
Stanislav Shwartsman
330bf62f61
added INVPCID instruction support
2011-09-16 20:06:23 +00:00
Stanislav Shwartsman
e2f0880f1c
support more than 32-bit cpu features vector
2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
02e1a0f23c
Merge lazy flags optimization by Darek Mihocka.
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I measure slight but consistent speedup of ~1-3% for all guests.
Tested: Windows XP/7 boot 32/64 bit, various Linux live CD
2011-09-12 19:36:53 +00:00
Stanislav Shwartsman
96cedbc756
continue handlers-chaining optimization: update time once per trace and not for every instruction
2011-09-06 15:35:39 +00:00
Stanislav Shwartsman
8099fd9efd
implemented alternative access to CR8: AMD feature. Lock CR0 -> CR8
2011-09-03 15:22:56 +00:00
Stanislav Shwartsman
1f5e036695
lzcnt/tzcnt bmi instructions implemented
2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
d2f7351be2
cpu.h cleanup + update msdev workspaces cpudb projects
2011-08-30 22:22:07 +00:00
Stanislav Shwartsman
dfd769a102
- Fixed compilation issue with cpu-level=5
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- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b
syscall/sysret are not supported outside long64 mode in Intel CPUs
2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
c30275016e
avx2 added broadcast from register
2011-08-29 21:00:25 +00:00
Stanislav Shwartsman
44241a1e56
- Added support for AVX and AVX2 instructions emulation, to enable configure
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with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
d841e82d87
MOVBE instruction exists only in memory form
2011-08-25 21:20:50 +00:00
Stanislav Shwartsman
002e7a3818
MSR_TSC_AUX is not available without RDTSCP
2011-08-21 19:09:35 +00:00
Stanislav Shwartsman
371dc200fc
Remove the 'trace' debug feature fro the main stream (which now runs with handlers chaining) and this way reduce each handler size.
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Another 3% speedup on WinXP boot on top of handlers chaining + reduction of Bochs binary size by 45K.
2011-08-21 17:04:21 +00:00
Stanislav Shwartsman
13feb0772a
- 10% emulation speedup with handlers chaining optimization implemented. The
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feature is enabled by default when configure with --enable-all-optimizations
option, to disable handlers chaining speedups configure with
--disable-handlers-chaining
2011-08-21 14:31:08 +00:00
Stanislav Shwartsman
dd79431702
rename AVX handlers - match their real operands
2011-08-20 15:10:18 +00:00
Stanislav Shwartsman
b8b63ac6ea
compile CPUDB to separate library
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reduce compile-time dependencies
2011-08-18 18:55:22 +00:00
Stanislav Shwartsman
ed9b8478b5
undo RDTSC commit
2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf
separate TSC to uniq feature that can be disabled in CPU configuration
2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
b69f728246
Fixed internal debugger part of the bug:
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#3312237 stepN command might be not working properly
The problem still can be exists for SMP.
2011-08-17 19:51:32 +00:00
Stanislav Shwartsman
6606c62439
cr4 available since Pentium only
2011-08-16 16:49:04 +00:00
Stanislav Shwartsman
6344c6a719
Added P2 Klamath CPUID + some code reorg again
2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
f15bc6cf75
support for NX outside of x86-64.
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required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
1b27438146
cleanups + small code reorg
2011-08-10 20:31:29 +00:00
Stanislav Shwartsman
360481b391
infastructure for RDMSR/WRMSR control for cpuid class
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now the order is going to be:
1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
2ee0029749
extract ffxsr support to separate CPU feature
2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
075db389a9
added atom n270 cpuid + small fixes
2011-08-03 17:49:49 +00:00
Stanislav Shwartsman
e48765a511
VMX fixed, cleanups
2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
4ac67ec386
compilation when cu_level < 4
2011-07-29 15:24:32 +00:00
Stanislav Shwartsman
78327d3e5e
First step toward completely configurable CPU.
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Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
d11114ac19
Patch for emulating target with larger memory than host has available by Gary Cameron.
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The patch was posted in mailing list at Thu 6/16/2011.
Desription for CHANGES:
- Memory
- Added new configure option which enables RAM file backing for large guest
memory with a smaller amount host memory, without causing a panic when
host memory is exhausted (patch by Gary Cameron). To enable configure with
--enable-large-ramfile option.
2011-07-22 17:46:06 +00:00
Stanislav Shwartsman
b4118fcbfe
correct natural width VMX field read/write len
2011-07-21 20:58:54 +00:00
Stanislav Shwartsman
a69eeb13f3
move cpuid defs to cpuid.h
2011-07-19 21:14:07 +00:00
Stanislav Shwartsman
cddd1e3758
MONITOR/MWAIT: Do monitor on cache line granularity only + bugfix with possible TLB caching of monitored line
2011-07-18 21:44:22 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
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Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
909e750549
Implemented VMX preemption timer VMEXIT control (patch by Jianan Hao)
2011-07-03 15:59:48 +00:00
Stanislav Shwartsman
08ba847ce4
fix bug inserted with prev commit + cleanup
2011-06-28 16:04:40 +00:00
Stanislav Shwartsman
87953711b1
cleanup in mmx code
2011-06-26 19:31:42 +00:00
Stanislav Shwartsman
2f582db722
compile less stuff for cpu-level=5
2011-06-26 19:15:30 +00:00
Stanislav Shwartsman
beafa7c88b
improved x86 hw code bp handling
2011-06-24 13:38:34 +00:00
Stanislav Shwartsman
31be835056
bugfix + rename function
2011-06-14 19:56:28 +00:00
Stanislav Shwartsman
ef38c9e235
fix decode for VCVTPH2PS
2011-06-11 18:26:05 +00:00
Stanislav Shwartsman
8399dee24c
implemented AVX float16 convert instructions
2011-06-11 13:12:32 +00:00
Stanislav Shwartsman
3f075d1ddf
disasm for invpcid
2011-06-10 12:49:52 +00:00
Stanislav Shwartsman
29e3f6e762
remove trace cache disabled mode from the code. next step going to be - introducing new optimization features based on trace cache
2011-06-01 20:34:04 +00:00
Stanislav Shwartsman
04e9254e2c
AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A
2011-05-30 20:15:50 +00:00
Stanislav Shwartsman
ee3f9e36cb
Implemented Supervisor Mode Execution Protection (SMEP)
2011-05-29 16:28:26 +00:00
Stanislav Shwartsman
de95fa8e13
more changes towards configurable cpuid
2011-05-24 18:23:28 +00:00
Stanislav Shwartsman
92bb77ef1d
Merge patch from SF tracker:
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[3298173] Breakpoint on VMEXIT event by Jianan Hao
Patch description:
The patch provides a new command "vmexitbp" to set breakpoint when VM guest exit. The simulation will be stopped before first HOST mode instruction is executed.
Usage:
Type "vmexitbp" in debugger command window to switch it on/off (similar to modebp).
Currently, the patch has no corresponding interface on GUI debugger. Someone may add it if interested.
2011-05-06 08:19:03 +00:00
Stanislav Shwartsman
a02ddb36d2
undo a change from 2 weeks ago that cause correctness failure
2011-05-06 08:03:45 +00:00
Stanislav Shwartsman
c44f82f4ac
small cleanup
2011-04-25 20:26:22 +00:00
Stanislav Shwartsman
a02d8cfe67
cleanups, simplications, copyright updates
2011-04-23 20:39:27 +00:00
Stanislav Shwartsman
4f46b6eab2
bcd flags handling change
2011-04-23 10:49:36 +00:00
Stanislav Shwartsman
a1b523dacd
warning fix
2011-04-22 15:18:05 +00:00
Stanislav Shwartsman
5230bd27ee
added/fixed comments
2011-04-21 15:51:36 +00:00
Stanislav Shwartsman
024a1ace38
move X2APIC to be .bochsrc option, rework of the cpuid code
2011-04-21 13:27:42 +00:00
Stanislav Shwartsman
6e79fdfb1e
optimize data hw breakpoint
2011-04-09 05:12:28 +00:00
Stanislav Shwartsman
4de76b0571
introduced victim cache for a trace cache structure.
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Allows to significantly cut trace cache miss latenct and find data in victim cahe instead of redoding it
8 entries VC in parallel with direct map 64K entries
2011-03-25 23:06:34 +00:00
Stanislav Shwartsman
dd36d3c754
fixed code breakpoint hit
2011-03-24 19:06:58 +00:00
Stanislav Shwartsman
31dd6a70db
small cleanups
2011-03-20 21:16:45 +00:00
Stanislav Shwartsman
7664c55b08
first fixups after AVX
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(and for AVX)
2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
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many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
16021a0ddb
rename model_specific.h to be cpuid.h
2011-03-19 17:35:18 +00:00
Stanislav Shwartsman
63fe52f601
accessors for DR6 and DR7 fields
2011-03-15 20:20:15 +00:00
Stanislav Shwartsman
edd7c2d787
small reorg in cpuid code
2011-03-14 20:28:16 +00:00
Stanislav Shwartsman
acd320699d
small cleanups
2011-03-14 06:25:54 +00:00
Stanislav Shwartsman
2bef4597d6
volatile is redundant here
2011-03-03 19:51:29 +00:00
Stanislav Shwartsman
acb83acfa7
Fixed decoding of CRC32 instr
2011-02-26 20:43:11 +00:00
Stanislav Shwartsman
66682a0ba7
added ability to configure CPU family and model through .bochsrc
2011-02-25 15:05:48 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
b5ebe5865e
Fixes for incoming bug report, missed changes in CVS, repository fixups and etc
2011-02-11 09:56:23 +00:00
Stanislav Shwartsman
498b591452
quick code reorg that gives 3% speedup
2011-01-26 11:48:13 +00:00
Stanislav Shwartsman
f1821fa3bf
SMC invalidation only for traces that were really affected by SMC store
2011-01-23 15:54:54 +00:00
Stanislav Shwartsman
12005d92cf
split more SSE ops
2011-01-21 19:46:44 +00:00
Stanislav Shwartsman
0de2b305bc
split SSE opcode
2011-01-21 19:21:16 +00:00
Stanislav Shwartsman
a31103e7d8
optimize fetchdecode tables - part2
2011-01-21 16:07:51 +00:00
Stanislav Shwartsman
fbc9b8b190
phase1 of opcode tables optimization
2011-01-20 16:24:42 +00:00
Stanislav Shwartsman
8c5c078b13
optimize sse and mmx code
2011-01-16 20:42:28 +00:00
Stanislav Shwartsman
45f0c72385
remove duplicated instr
2011-01-15 15:17:28 +00:00
Stanislav Shwartsman
fcdadabbc4
Rewritten SMC handling, removed pageWriteStamp, now trace fetch chck only for pAddr
2011-01-12 18:49:11 +00:00
Stanislav Shwartsman
a80b44b6db
split more sse ops
2011-01-09 20:18:02 +00:00
Stanislav Shwartsman
c5aca5ac21
move function to inline
2011-01-08 19:50:22 +00:00
Stanislav Shwartsman
37204c0aaa
split more SSE ops
2011-01-08 12:28:25 +00:00
Stanislav Shwartsman
a1bc92a46b
split more SSE opcodes
2011-01-08 11:20:29 +00:00
Stanislav Shwartsman
2946d0ac26
split more SSE ops
2010-12-30 21:45:39 +00:00
Stanislav Shwartsman
f9f868247a
split more SSE ops
2010-12-30 20:35:10 +00:00
Stanislav Shwartsman
fd5558d4be
another way to implement this op
2010-12-26 20:54:23 +00:00
Stanislav Shwartsman
25b1e2e58d
split more SSE ops
2010-12-26 20:41:47 +00:00
Stanislav Shwartsman
f705cbbc63
rename functions
2010-12-25 19:34:43 +00:00
Stanislav Shwartsman
1bd512e98d
split more SSE ops, optimizations in MMX code
2010-12-25 17:04:36 +00:00
Stanislav Shwartsman
c005444d5b
split more SSE opcodes
2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
040a8e1a3a
split bunch of SSE opcodes
2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
43600f3756
complete rework of SSE code
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next step - split all SSE opcodes by ModC0
2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
29a674e520
split rd/wr CR opcodes for simplicity
2010-12-19 22:36:19 +00:00
Stanislav Shwartsman
c7017b1c05
simplification
2010-12-19 21:41:15 +00:00
Stanislav Shwartsman
4a85a8680e
SSE optimization
2010-12-19 07:06:40 +00:00
Stanislav Shwartsman
48d94d6dc3
optimization
2010-12-18 11:58:16 +00:00
Stanislav Shwartsman
36291b0b1d
accessor to upper part of 64-bit reg
2010-11-12 20:46:59 +00:00
Stanislav Shwartsman
e6981218dc
next step for fully configurable CPU + more optimal VMX execution
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- check at startup time which VMX fields are accessible
- next step: simplify VMREAD and VMWRITE instructions - eliminate switch statements
2010-11-11 21:41:03 +00:00
Stanislav Shwartsman
5ea2591cd9
fixes
2010-10-07 20:40:01 +00:00
Stanislav Shwartsman
6d089dd238
changed CPUID constants to defines
2010-10-07 16:39:31 +00:00
Stanislav Shwartsman
75f2ae9c18
fetchdecode simplification rework
2010-09-25 09:55:40 +00:00
Stanislav Shwartsman
1107ce138e
small fetchdecode optimization
2010-09-07 19:54:50 +00:00
Stanislav Shwartsman
31e8bfc5a7
Fixed fsgsbase cpuid bit
2010-07-22 20:19:00 +00:00
Stanislav Shwartsman
91ac0df65c
implemented GS/FS BASE access instructions published in _319433-007.pdf document
2010-07-22 16:41:59 +00:00
Stanislav Shwartsman
7f7c249934
disasm and some cpuid code according to recently published AVX_319433-007.pdf document
2010-07-22 15:12:08 +00:00
Stanislav Shwartsman
8d8d1590f5
fetchdecide rework for AVX (0xF3 SSE prefix encoded as 2 in VEX)
2010-05-23 19:17:41 +00:00
Stanislav Shwartsman
1c00193616
cleanup
2010-05-22 10:43:39 +00:00
Stanislav Shwartsman
fff0a79aea
a little simpler fetchdecode
2010-05-21 21:17:32 +00:00
Stanislav Shwartsman
3dfcfd0ccd
Split shift opcodes | optimize SAR opcode
2010-05-18 07:28:05 +00:00
Stanislav Shwartsman
74b87d2b68
fixes for CPUID and alloweds bits in CRs
2010-05-12 21:33:04 +00:00
Stanislav Shwartsman
d849cdf128
- Determine and select max physical address size automatically at
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configure time:
- 32-bit physical address for 386/486 guests
- 36-bit physical address for PSE-36 enabled Pentium guest
- 40-bit physical address for PAE enabled P6 or later guests
2010-05-12 14:55:12 +00:00
Stanislav Shwartsman
49934bc853
cache page split instructions
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next step - cache page split traces
2010-05-08 08:30:04 +00:00
Stanislav Shwartsman
b0d5142e18
comp fixes
2010-05-06 21:46:39 +00:00
Stanislav Shwartsman
ca95477b7f
Implement x86-64 PCID extension
2010-04-29 19:34:32 +00:00
Stanislav Shwartsman
1c2fa8cd0c
move 1G_pages support to runtime option
2010-04-24 09:36:04 +00:00
Stanislav Shwartsman
ea95341e05
compile fix
2010-04-22 18:48:39 +00:00
Stanislav Shwartsman
749d6c33d2
relocate lazy_flags code from cpu.h
2010-04-15 05:51:00 +00:00
Stanislav Shwartsman
689ecc57dd
split 2 more SSE opcodes
2010-04-08 17:35:32 +00:00
Stanislav Shwartsman
6e1204cb84
Merged X2APIC + X2APIC virtualization
2010-04-08 15:50:39 +00:00
Stanislav Shwartsman
df7db31fb4
EPT + VPID - VMXx2 support
2010-04-07 17:12:17 +00:00
Stanislav Shwartsman
c94e72d4d3
make lpf_mask smaller
2010-04-07 14:38:53 +00:00
Stanislav Shwartsman
21de4f8b8b
remove cr3_masked
2010-04-04 09:04:12 +00:00
Stanislav Shwartsman
7c42447c77
move secondary VMEXEC controls to -enable-vmx=2 option
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EPT coming next
2010-04-03 07:30:23 +00:00
Stanislav Shwartsman
d39d485ece
changes variable name to better one
2010-04-03 05:59:07 +00:00
Stanislav Shwartsman
01de3e1926
PEXTRB/W/D/EXTRACTPS fixed
2010-04-02 19:03:47 +00:00
Stanislav Shwartsman
2efb11f2bc
fixes
2010-03-30 18:12:19 +00:00
Stanislav Shwartsman
64e9ff6aff
add PDPTRS into param tree
2010-03-25 22:04:31 +00:00
Stanislav Shwartsman
f5ce2a7639
split crreg access functions to separate file
2010-03-25 21:33:07 +00:00
Stanislav Shwartsman
e88e168081
bswap undefined behavior
2010-03-19 10:00:48 +00:00
Stanislav Shwartsman
d0bd30e4b9
optimization
2010-03-18 15:19:16 +00:00
Stanislav Shwartsman
78badcbde4
cleanup
2010-03-17 21:55:19 +00:00
Stanislav Shwartsman
79466dffe2
apic virtualization + vmx fixes
2010-03-16 14:51:20 +00:00
Stanislav Shwartsman
1c6cc35b06
fixed TPR shadow
2010-03-15 14:18:36 +00:00
Stanislav Shwartsman
6134283932
vmx update
2010-03-15 13:54:54 +00:00
Stanislav Shwartsman
3c1b8a63d7
VMX bugfix
2010-03-15 13:22:14 +00:00
Stanislav Shwartsman
cffe32dd2c
remove unused param from exception() call
2010-03-14 15:51:27 +00:00
Stanislav Shwartsman
36b0b3c682
compilation fixes
2010-03-13 21:06:56 +00:00
Stanislav Shwartsman
6dd9c7d5f5
ifdef
2010-03-12 20:30:12 +00:00
Stanislav Shwartsman
11de02bd89
MONITOR/MWAIT: rewritten MONITOR/MWAIT implementation from scratch
2010-03-07 09:16:24 +00:00
Stanislav Shwartsman
5d2c2879a7
IA32_FEATURE_CONTROL_MSR is implemented
2010-03-06 16:59:05 +00:00
Stanislav Shwartsman
189553d702
bugfix
2010-03-05 08:54:07 +00:00
Stanislav Shwartsman
01cfbdccbc
Move MMX to be runtime option
2010-03-01 18:53:53 +00:00
Stanislav Shwartsman
160d4bbded
Fixed typo
2010-03-01 17:35:49 +00:00
Stanislav Shwartsman
5b6a14656d
Make XSAVE as runtime option
2010-02-26 22:53:43 +00:00
Stanislav Shwartsman
927c3594d6
enable compilation with CPU_LEVEL <= 6
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converted SEP to runtime option as well
2010-02-26 11:44:50 +00:00
Stanislav Shwartsman
033a20b3b2
allow to configure CPU features at runtime - implemened on example of SSE/AES/MOVBE/POPCNT
2010-02-25 22:04:31 +00:00
Stanislav Shwartsman
70dc124b3a
1st step of moving CPU options to runtime
2010-02-24 19:27:51 +00:00
Stanislav Shwartsman
5f89b554aa
split few more opcodes
2010-02-10 17:21:15 +00:00
Stanislav Shwartsman
c841eaa953
fixes and cleanups in disasm and decoder
2010-02-09 19:44:25 +00:00
Stanislav Shwartsman
dc02d836ce
Fix POPCNT decode tables
2010-01-29 10:16:28 +00:00
Stanislav Shwartsman
7d7f18b585
cleanup
2010-01-19 14:43:47 +00:00
Stanislav Shwartsman
e59ff3d779
cleanup
2009-12-28 09:26:22 +00:00
Stanislav Shwartsman
6f8f69e5bb
set/get_ar_byte not need to be CPU members
2009-12-27 16:53:35 +00:00
Stanislav Shwartsman
d779842da3
added ability to modify sregs from bochs debugger
2009-12-27 16:38:09 +00:00
Stanislav Shwartsman
5579bdfc55
removed unused param
2009-12-22 12:11:09 +00:00
Stanislav Shwartsman
33ad9296ff
bugfix
2009-12-22 11:58:26 +00:00
Stanislav Shwartsman
30c9eef6f9
small optimization
2009-12-21 13:38:06 +00:00
Stanislav Shwartsman
c403090327
! Implemented PCLMULQDQ AES instruction
2009-12-20 09:00:40 +00:00
Stanislav Shwartsman
edaf19f0a1
Split MOVQ_PqQq opcode
2009-12-14 11:55:42 +00:00
Stanislav Shwartsman
bd60e0264c
change Copyright to Bochs Project
2009-12-04 16:53:12 +00:00
Stanislav Shwartsman
604e7aa7ac
typo fix
2009-11-29 21:05:59 +00:00
Stanislav Shwartsman
2defc78bac
cleanups
2009-11-29 21:01:26 +00:00
Stanislav Shwartsman
553ca8af01
split more SSE ops
2009-11-25 20:49:47 +00:00
Stanislav Shwartsman
6819ab4eb7
split sse opcodes
2009-11-23 18:21:23 +00:00
Stanislav Shwartsman
5bfbc9df5f
RETF bug fuxed
2009-11-19 20:00:35 +00:00
Stanislav Shwartsman
71bb10f98c
move ignore-bad-msrs to runtime option in ,bochsrc
2009-11-13 15:55:46 +00:00
Stanislav Shwartsman
3e3cfc610f
cleanup
2009-10-31 19:16:09 +00:00
Stanislav Shwartsman
6f0db17b08
fixed #DB on rpeat instructions
2009-10-30 09:13:19 +00:00
Stanislav Shwartsman
98b51805d5
updates for Bochs debugger
2009-10-29 15:49:50 +00:00
Stanislav Shwartsman
78e4b3d616
split SSE move instructions
2009-10-24 11:17:51 +00:00
Stanislav Shwartsman
b80249dfcb
added PANIC for unsupported VMX feature
2009-10-22 13:33:13 +00:00
Stanislav Shwartsman
da4722e257
optimize sr params
2009-10-16 18:29:45 +00:00
Stanislav Shwartsman
5909ef1494
loading of null segment with RPL != 0
2009-10-12 20:50:14 +00:00
Stanislav Shwartsman
6d6bf4a65e
code optimization for future
2009-10-08 18:07:50 +00:00
Stanislav Shwartsman
d9f701ddb0
LSL/LAR fixed in 64-bit mode
2009-10-02 16:09:08 +00:00
Stanislav Shwartsman
85f1004ce0
implemented TPR shadow feature for VMX
2009-09-30 05:57:21 +00:00
Stanislav Shwartsman
d273ae14b0
rework in paging.cc
2009-09-26 06:06:35 +00:00
Stanislav Shwartsman
8e3276cf14
split opcodes by ModC0
2009-08-22 11:47:42 +00:00
Stanislav Shwartsman
8a95120e12
deprecate --enable-vme option, now it will be supported iff CPU_LEVEL >= 5 (like in real life)
2009-08-10 15:44:50 +00:00
Stanislav Shwartsman
66c4654418
segment desriptor 'A' bit handling fixes
2009-07-27 05:52:28 +00:00
Stanislav Shwartsman
f2d84e1604
Fixed VMREAD/VMWRITE of 16-bit vmx fields
2009-07-21 11:56:26 +00:00
Stanislav Shwartsman
733491871d
copy/paste typo fix
2009-06-15 15:10:05 +00:00
Stanislav Shwartsman
cd445195dd
cleanup configure options. All paging related stuff is now automatically set/unset according to cpu-level option.
...
Related configure options (--enable-pae, --enable-mtrr, --enable-global-pages, --enable-large-pages) are deprecated.
Less configure options - less configure problems :)
2009-06-15 09:30:56 +00:00
Stanislav Shwartsman
716465fb16
bugfix: Half-baked VMX Link Pointer state checking.
2009-06-06 10:21:49 +00:00
Stanislav Shwartsman
03ba2ec988
implement pdptr checks in legacy PAE mode
2009-05-31 07:49:04 +00:00
Stanislav Shwartsman
222129db4b
Rewritten long mode page walk - large code cleanup and few bugfixes
2009-05-30 15:09:38 +00:00
Stanislav Shwartsman
3d7bbf4356
fixed VMXON pointer concept
2009-05-28 08:26:17 +00:00
Stanislav Shwartsman
847179fd13
mtrr reverved bits check
2009-05-21 13:25:30 +00:00
Stanislav Shwartsman
efc413d2b4
VMX fixes
2009-05-21 10:39:40 +00:00
Stanislav Shwartsman
aac70fdf25
faster vmenter/vmexit
2009-05-03 13:02:14 +00:00
Stanislav Shwartsman
78418c6a74
removed cr1 from cpu
2009-05-01 09:32:46 +00:00
Stanislav Shwartsman
89f057ae7b
x87 fix
2009-04-27 14:00:55 +00:00
Stanislav Shwartsman
012b3a2e89
Eliminate code duplication
2009-04-14 13:43:21 +00:00
Stanislav Shwartsman
e0833381d5
Fixed priority between #NP and #GP
2009-04-14 09:23:36 +00:00
Stanislav Shwartsman
4fc66aab31
Fixes for compilation by Visual Studio 2008
2009-04-07 16:12:19 +00:00
Stanislav Shwartsman
9d4c24b6a3
Split instruction 32/64
2009-04-06 18:44:28 +00:00
Stanislav Shwartsman
153f86b1a8
save/restore mwait status correctly
2009-04-05 19:38:44 +00:00
Stanislav Shwartsman
fcb51dc168
oops, this break max_instr_count feature
2009-03-26 10:24:10 +00:00
Stanislav Shwartsman
043be27c2c
M$ comilerr can't optimize very good functions with long_jmp inside
2009-03-26 09:28:49 +00:00
Stanislav Shwartsman
e5be60be64
Fixed lazy flags bug I added in one of my prev merges
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ICACHE code reorganization
2009-03-22 21:12:35 +00:00
Stanislav Shwartsman
c3392488b5
reorganize cpu debugger support, less function, faster code
2009-03-17 19:40:26 +00:00
Stanislav Shwartsman
4470c6a1c8
make ICACHE always enabled option and deprecate it in the configure script
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Trace cache still can be turned off
2009-03-13 18:48:08 +00:00
Stanislav Shwartsman
10c8d8ea33
improve lazy flags after ADD instruction
2009-03-13 18:26:10 +00:00
Stanislav Shwartsman
9417cbee63
- cpu optimizations 9remove redundant, add new)
2009-03-13 18:02:33 +00:00
Stanislav Shwartsman
9e723a044f
- Added configure option to enable/disable A20 pin support. Disabling the
...
A20 pin support slightly speeds up the emulation.
- small code cleanup
2009-03-10 16:28:01 +00:00
Stanislav Shwartsman
6fe0b40b44
move a20 handling into getHostAddr method of BX_MEM
2009-03-08 21:23:40 +00:00