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310 Commits

Author SHA1 Message Date
Stanislav Shwartsman
58bbf0d0b1 compilation fix for 386 2010-04-03 19:21:07 +00:00
Stanislav Shwartsman
eab8826173 restore back some code - optimization conflicting with EPT implementation 2010-04-03 18:00:30 +00:00
Stanislav Shwartsman
a445b5c4f3 optimization + fix 2010-04-03 16:52:33 +00:00
Stanislav Shwartsman
7c42447c77 move secondary VMEXEC controls to -enable-vmx=2 option 
EPT coming next
 2010-04-03 07:30:23 +00:00
Stanislav Shwartsman
8260358afe removed redundant check 2010-04-02 16:56:59 +00:00
Stanislav Shwartsman
b049646621 compilation fix for x86_64 disable 2010-04-01 20:53:55 +00:00
Stanislav Shwartsman
a625abaaf0 small fixes 2010-04-01 20:08:57 +00:00
Stanislav Shwartsman
585cc3492b paging similication 2010-04-01 20:06:09 +00:00
Stanislav Shwartsman
9224bf60aa paging phase 3 2010-04-01 12:23:52 +00:00
Stanislav Shwartsman
6f7b68e1ca paging redo - step2 2010-04-01 11:53:22 +00:00
Stanislav Shwartsman
1b24ebe9bb paging anti-code-duplication, phase1 2010-04-01 05:26:20 +00:00
Stanislav Shwartsman
24bd0399d2 fixed dbg paging lookup 2010-03-31 14:17:51 +00:00
Stanislav Shwartsman
2614b3ca2f continue NX fix 2010-03-30 16:56:41 +00:00
Stanislav Shwartsman
64e9ff6aff add PDPTRS into param tree 2010-03-25 22:04:31 +00:00
Stanislav Shwartsman
f5ce2a7639 split crreg access functions to separate file 2010-03-25 21:33:07 +00:00
Stanislav Shwartsman
4400edc746 fix for 2795115 NX fault could be missed 2010-03-23 19:58:20 +00:00
Stanislav Shwartsman
da656bf93d optimization for paging disable mode + preparing for future 2010-03-19 17:00:05 +00:00
Stanislav Shwartsman
79466dffe2 apic virtualization + vmx fixes 2010-03-16 14:51:20 +00:00
Stanislav Shwartsman
cffe32dd2c remove unused param from exception() call 2010-03-14 15:51:27 +00:00
Stanislav Shwartsman
927c3594d6 enable compilation with CPU_LEVEL <= 6 
converted SEP to runtime option as well
 2010-02-26 11:44:50 +00:00
Stanislav Shwartsman
bd60e0264c change Copyright to Bochs Project 2009-12-04 16:53:12 +00:00
Stanislav Shwartsman
3e3cfc610f cleanup 2009-10-31 19:16:09 +00:00
Stanislav Shwartsman
54cdee30c1 fix dbg method as well 2009-10-26 22:05:00 +00:00
Stanislav Shwartsman
220c893c6d remove dbg print 2009-10-26 21:19:23 +00:00
Stanislav Shwartsman
40352dc310 fix 4M paging 2009-10-26 21:16:04 +00:00
Stanislav Shwartsman
e9967c6b83 fixed 4M paging 2009-10-24 21:00:43 +00:00
Stanislav Shwartsman
b6155ef5ca compilation fix 2009-10-03 11:39:29 +00:00
Stanislav Shwartsman
a7f3038cc4 cleanups + fix 2009-09-26 13:50:09 +00:00
Stanislav Shwartsman
e05040e891 rework in paging.cc - phase1 2009-09-26 06:05:23 +00:00
Stanislav Shwartsman
e5daa4abee bugfiX 2009-09-25 14:25:24 +00:00
Stanislav Shwartsman
c940141323 bugfix 2009-09-17 05:28:51 +00:00
Stanislav Shwartsman
7a473a14f3 Revert incorrect changE 2009-06-15 19:05:29 +00:00
Stanislav Shwartsman
26a1cef63b removed redundant (now) compilation directives 2009-06-15 09:34:49 +00:00
Stanislav Shwartsman
cd445195dd cleanup configure options. All paging related stuff is now automatically set/unset according to cpu-level option. 
Related configure options (--enable-pae, --enable-mtrr, --enable-global-pages, --enable-large-pages) are deprecated.
Less configure options - less configure problems :)
 2009-06-15 09:30:56 +00:00
Stanislav Shwartsman
03ba2ec988 implement pdptr checks in legacy PAE mode 2009-05-31 07:49:04 +00:00
Stanislav Shwartsman
222129db4b Rewritten long mode page walk - large code cleanup and few bugfixes 2009-05-30 15:09:38 +00:00
Stanislav Shwartsman
4fc66aab31 Fixes for compilation by Visual Studio 2008 2009-04-07 16:12:19 +00:00
Stanislav Shwartsman
a0b1fda178 bugfixes 2009-03-27 16:42:21 +00:00
Stanislav Shwartsman
6fe0b40b44 move a20 handling into getHostAddr method of BX_MEM 2009-03-08 21:23:40 +00:00
Stanislav Shwartsman
e6685b3557 Fixed comp err with APIC disabled 2009-02-23 17:09:39 +00:00
Stanislav Shwartsman
1b72e66bb3 support for apic global disable 
separate between I/O apic and local apic
 2009-02-18 22:25:04 +00:00
Stanislav Shwartsman
3a1852ea23 take local APIC read/write access into CPU class from BX_MEM (needed for APIC virtualization later) 2009-02-17 19:20:47 +00:00
Stanislav Shwartsman
7c0582e4ea Some fixes for X86-64 OFF mode 2009-02-04 16:05:47 +00:00
Stanislav Shwartsman
f8185a6bc6 Added Intel VMX emulation to Bochs CPU 2009-01-31 10:43:24 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
a794bef607 optimize invlpg for split large pages 2008-12-19 16:03:25 +00:00
Stanislav Shwartsman
2682738968 added ifdefs around 1G paging implementation 2008-12-11 21:30:37 +00:00
Stanislav Shwartsman
a2e07ff971 - Removed --enable-guest2hos-tlb configure option. The option will be 
always enabled for any Bochs configuration.
 2008-12-11 21:19:38 +00:00
Stanislav Shwartsman
69bd21bf1d 1G pages support for CPU 2008-12-11 21:00:01 +00:00
Stanislav Shwartsman
5174f9fe82 Fixed debian i386 image freeze 2008-12-08 20:01:26 +00:00
Stanislav Shwartsman
d7fa44d270 optimize code access detection 2008-12-05 22:34:42 +00:00
Stanislav Shwartsman
ef36cec716 moving definition to config.h 2008-12-01 19:35:25 +00:00
Stanislav Shwartsman
e402062499 -Fixes for INVLPG 2008-11-29 19:28:10 +00:00
Stanislav Shwartsman
3d97374ce8 Some fixes for functionality 2008-09-24 10:39:35 +00:00
Stanislav Shwartsman
991ae348cb Clean invalidate_prefetch_q when not needed 2008-08-23 13:55:37 +00:00
Stanislav Shwartsman
5e92a1642d Fixed compilation errors, added BX_ASSERT in paging.cc 2008-08-18 05:20:23 +00:00
Stanislav Shwartsman
e2fa98b629 - Fixed TLB flush on CR3 change - flush all pages is CR4.PGE is OFF 2008-08-16 15:35:35 +00:00
Stanislav Shwartsman
5eb845763e Fixed corner case problem cause by my prev optimization 2008-08-15 14:30:50 +00:00
Stanislav Shwartsman
aea946b4a3 One more change to speedup memory access through HostPtr check 2008-08-14 22:26:15 +00:00
Stanislav Shwartsman
dcb82ec4bf Optimize TLB flush methods 2008-08-13 21:51:54 +00:00
Stanislav Shwartsman
cddcdccd99 Fixed paging bug 2008-08-10 20:32:00 +00:00
Stanislav Shwartsman
5dd02b26e3 Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before 2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
bbf02a8bc5 More clean rewrite of the TLB access bits 2008-08-07 22:14:38 +00:00
Stanislav Shwartsman
67eb13bf24 Fixed bug in PDPE cache implementation 2008-08-04 14:46:28 +00:00
Stanislav Shwartsman
4808a0d581 Fixed accessBits algebra 2008-08-04 05:30:37 +00:00
Stanislav Shwartsman
6398ebb1d4 First step of access bits cleanup and optimization - no perf gain yet 2008-08-03 19:53:09 +00:00
Stanislav Shwartsman
67f302352c Implement PDPE cache to support faster PAE paging tranlsation 2008-08-01 13:28:44 +00:00
Stanislav Shwartsman
709d74728d Call #UD exception directly instead of UndefinedOpcode function - for future use 2008-07-13 15:35:10 +00:00
Stanislav Shwartsman
c1f308d80d Push error code if segment violation occurs when pushing arguments into a new stack 2008-06-25 02:28:31 +00:00
Stanislav Shwartsman
a0e66d0e4c fixed variable name 2008-06-14 16:55:45 +00:00
Stanislav Shwartsman
b7480b3e6f - Fixed x86 data breakpoint match when breakpoint length is 8 bytes 
- FIxed x86 data breakpoint in paging disabled mode
 2008-06-02 18:41:08 +00:00
Stanislav Shwartsman
5c75e54d45 cleanup and small optimization for non-paging mode 2008-05-30 16:58:47 +00:00
Stanislav Shwartsman
6c5f82c4c8 - Fixed bug in global pages TLB invalidation 2008-05-30 12:14:00 +00:00
Stanislav Shwartsman
d76297d01e Fixed compilation err 2008-05-23 17:58:42 +00:00
Stanislav Shwartsman
3619c0f6b4 Some changes to make x86-debugger feature working back 2008-05-23 17:49:46 +00:00
Stanislav Shwartsman
3f1e436926 Removed unused variables in bx_dbg struct 2008-05-23 14:04:45 +00:00
Stanislav Shwartsman
4e091f2a3a Improved debug prints 2008-05-21 21:38:59 +00:00
Stanislav Shwartsman
82d8e9a3b0 Fixed compilation warning 2008-05-19 20:05:03 +00:00
Stanislav Shwartsman
4e5d10d02e Code reorganization + small bug fixes in translate linear code 2008-05-19 18:10:32 +00:00
Stanislav Shwartsman
c3f96973ba Added debug prints 2008-05-12 19:19:03 +00:00
Stanislav Shwartsman
d934190370 Fixed data type for cr3_masked 2008-05-11 19:58:41 +00:00
Stanislav Shwartsman
4a76bd2169 Fixed setting of reserved bits in CR3 register 2008-05-11 19:36:06 +00:00
Stanislav Shwartsman
56a44d675b Fixed potential memory overflow in dbg paging function 2008-05-10 22:11:48 +00:00
Stanislav Shwartsman
6ebae41ad7 print physcial address with special format - preparations for 64-bit physical address emu 2008-05-09 22:33:37 +00:00
Stanislav Shwartsman
ed4be45a8b Split shift/rotate opcodes in 32-bit mode and 64-bit mode 2008-05-02 22:47:07 +00:00
Stanislav Shwartsman
67e534832b Remove from CPU reference to MEM object - it is only one and could be static 2008-04-27 19:49:02 +00:00
Stanislav Shwartsman
9047c9be96 Support for reserved bits checking in paging 
Check for page is in DTLB before invalidating by INVLPG
 2008-04-25 20:08:23 +00:00
Stanislav Shwartsman
3c7949948b - Added >32bit physical address PANIC in PSE mode with 4M paging 
- Fixed LAR/LSL instructions in 64-bit mode
 2008-04-22 22:05:38 +00:00
Stanislav Shwartsman
c09934f90a some small cleanup in paging code 2008-04-21 20:17:45 +00:00
Stanislav Shwartsman
359eb92c73 More fixes for CPU emulation 2008-04-19 20:00:28 +00:00
Stanislav Shwartsman
e10bd0b7a5 tasking - read state first and only when store state in new TSS 
paging - fixed data for trace-mem callbacks
 2008-04-19 14:13:43 +00:00
Stanislav Shwartsman
bdaef81603 Added debugger memory trace functionality. Enable by 'trace-mem on' command 2008-04-19 13:21:23 +00:00
Stanislav Shwartsman
20a8bf03ad Added comments for >32 bit physical address error message 2008-04-11 14:30:15 +00:00
Stanislav Shwartsman
fea49bb270 Fixed linear address wrap in legacy (not long64) mode 2008-04-07 18:39:17 +00:00
Stanislav Shwartsman
90f1973bef Removed BX_USE_TLB - TLB is always used, only Guest2HostTLB is optional feature 
Use Guest2HostTLB in prefetch code for IFETCHES - speedup above 3%
 2008-04-05 20:41:00 +00:00
Stanislav Shwartsman
e91409704f Convert EFER to val32 register, similar to other control registers 2008-03-31 20:56:27 +00:00
Stanislav Shwartsman
3f2487a0af Enabled tracing cross repeated instructions 2008-03-31 18:53:08 +00:00
Stanislav Shwartsman
b5f5e01f7e added assert to paging.cc 2008-03-29 21:12:11 +00:00
Stanislav Shwartsman
f3a91710e4 Split access_linear to access_read_linear and access_write_linear 2008-03-29 18:18:08 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
cdcd7522aa Added RIP to the GPR register file as lst register 
This allowed to optimize (read - remove) two more BxResolve methods in 64-bit mode
+ Some white space cleanup
 2008-02-15 19:03:54 +00:00
Stanislav Shwartsman
8d7410a852 Canonical check have higher priority than #AC check 2008-02-11 20:52:10 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
37fbb82baa Cleanups. Move bxInstruction_c definition to separate file instr.h 2008-01-29 17:13:10 +00:00
Stanislav Shwartsman
9be2d79f98 Added a parameter to INVLPD instrumentation call 2008-01-16 22:39:55 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
d891f0d8ec Fixed more VC2008 warnings - hopefully last ones 2007-12-30 17:53:12 +00:00
Stanislav Shwartsman
79fc57dec8 Fixed more VCPP2008 warnings 2007-12-26 23:07:44 +00:00
Stanislav Shwartsman
838fb2a048 Fixing V2008 warnings - they found a bug in sse_pfp.cc ! 2007-12-23 17:21:28 +00:00
Stanislav Shwartsman
a93b0afdbe Merge page split detection method suggested by Darek Mihocka 2007-12-21 10:33:39 +00:00
Stanislav Shwartsman
0af87ab63b Split string instructions according to the address size - simpler and faster 2007-12-17 18:48:26 +00:00
Stanislav Shwartsman
46366b5064 Speedup simulation by eliminating CPL==3 check from read/write_virtual* functions 2007-12-16 21:03:46 +00:00
Stanislav Shwartsman
f145f4c847 Unify BX_INSTR_MEM_READ and BX_INSTR_MEM_WRITE callbacks to single callback BX_INSTR_MEM_ACCESS 
Enable the callback with guest-to-host TLB enabled
Update instrumentation docs
 2007-12-13 21:30:05 +00:00
Stanislav Shwartsman
05a5923971 Merged Bochs instrumentation patch by Lluis Vilanova 2007-12-13 17:16:21 +00:00
Stanislav Shwartsman
d739cca282 small cleanup 2007-12-06 18:35:33 +00:00
Stanislav Shwartsman
c58e95f611 Make hw breakpoint match check a function - normally it should be called from read/write_virtual as well 2007-12-03 20:49:24 +00:00
Stanislav Shwartsman
1af7010e50 Optimized memory access for 64-bit mode 
Starting convergence to new lazy flags scheme by Darek Mihocka (www.emulators.com). The new flags code is still being validated and perfected but I try to minimize the diff between 2 versionS
 2007-11-20 17:15:33 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
9dc471bbe5 Simplify Guest2HostTLB code 
Fixed APIC CPUID bit
 2007-11-11 20:44:07 +00:00
Stanislav Shwartsman
5fd21257de Remove qick TLBN invalidation code - it actually only could slow down emulation 2007-11-09 21:14:56 +00:00
Stanislav Shwartsman
2f5fa07af3 small speedups 2007-11-07 10:40:40 +00:00
Stanislav Shwartsman
e137560b14 Complete MONITOR/MWAIT implemntation (including monitoring of memory range) 
Fixed PANIC in read/write Cr/Dr - should #UD with unkown register used
 2007-11-01 18:03:48 +00:00
Stanislav Shwartsman
ce0e0287fb Naturally speedup repeat execution functions, fix TLB index calculations 2007-10-30 22:15:42 +00:00
Stanislav Shwartsman
2d981562c4 changes Bit32u -> bx_phy_address in dbg paging method 2007-10-08 20:45:30 +00:00
Stanislav Shwartsman
91e6ca8d5c Implemented MTRR support 
Fixes in #PF exception priority
 2007-09-20 17:33:35 +00:00
Stanislav Shwartsman
70f513b07b Make efer control MSR separate register 2007-09-10 20:47:08 +00:00
Stanislav Shwartsman
5ac1bb6646 rewrite page fault 2007-08-30 16:48:10 +00:00
Stanislav Shwartsman
38d1f39c77 Converted CR0 bits to one register similar to CR4 - a bit slower but helps with other features implemntation 2007-07-09 15:16:14 +00:00
Stanislav Shwartsman
c184a3a2ba Removed redundant mem-only checks - handled in fetchdecode now 2007-03-23 14:50:45 +00:00
Stanislav Shwartsman
dd00bc66d0 Fixed disasm in 64bit mode, added new accessor for printing 64bit values 2007-01-13 10:43:31 +00:00
Stanislav Shwartsman
905de565a9 Add debug prints for NX bit feature 2006-10-28 12:31:23 +00:00
Stanislav Shwartsman
e3da944cd3 Fixed TLB access code duplication 2006-10-04 19:47:24 +00:00
Stanislav Shwartsman
6c63e84d23 Fixed CR3 masking in long mode 
Added PANIC assertion of 32-bit physical address in PAE mode
cleanup
 2006-10-04 19:08:40 +00:00
Stanislav Shwartsman
3ab94305a0 1. Fixed bug report 
[ bochs-Bugs-1562172 ] TLB_init() fails to initialize priv_check array if USE_TLB 0
2. Paging is always exists for i386+
   To disable paging it is better to use normal model without special code, only by setting cr0.pg=0
 2006-09-20 17:02:20 +00:00
Stanislav Shwartsman
070d782ec8 Move paddr_valid param of dbg_xlate_linear2phy method to return value. 
This is much easier to use.
 2006-06-17 12:09:55 +00:00
Stanislav Shwartsman
deab206378 More useful debug prints 2006-06-09 22:39:50 +00:00
Stanislav Shwartsman
6c3420a18b Add debug prints before any #GP excepion which only possible to be generated 2006-06-09 22:29:07 +00:00
Stanislav Shwartsman
f93ab35357 Flush TLB for all CPUs when memory mapping information changed by system (A20 change, PAM write or similar events) 2006-04-29 17:21:49 +00:00
Stanislav Shwartsman
798c90ee85 Fixed comments 2006-04-26 14:05:28 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash: 
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
 2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
4fd9bd53c3 Change Bit32u -> bx_phy_address in memory 2006-03-28 16:53:02 +00:00
Stanislav Shwartsman
b8be848943 Use access_type param in getHostMemAddr, less efficient but no copy-paste at least 2006-03-26 19:39:37 +00:00
Stanislav Shwartsman
f347ab97bf Fixed CALL/JMP far through call gate 64 
Decode SWAPGS and RDTSCP instructions
Indent changes in fetchdecode
 2006-03-22 20:47:11 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU 
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
 2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
e297df457a Roll back the try to move Local APIC memory access to CPU. 
It was fast and fine but had serious correctness problems with RMW apic access
 2006-03-02 23:16:13 +00:00
Stanislav Shwartsman
5fad793989 move local apic handling to the access_linear function for the memory class. 
speedup the whole simulation by 2% !
 2006-03-01 22:32:24 +00:00
Stanislav Shwartsman
55ceecf79b Small optimization in icache page-write-stamp 2006-02-28 17:47:33 +00:00
Stanislav Shwartsman
8c91790680 Redefine registers accessors in cpu.h 
Change BxSupportPAE and BxSupportGlobalPages macros to Bochs style names
Set bx_cpu_id in BX_CPU_C constructor (safe way)
Backup cpu-level check for paging features at compile time (already checked in configure)
Some warnings and indent fixes
speed up get_segment_base method for x86-64 case
 2005-11-26 21:36:51 +00:00
Stanislav Shwartsman
8d9b5b7134 Fixed compilation error when PAE diasbled and BX_DEBUGGER enabled 
CVS patch by shirokuma #SF 1359011
 2005-11-17 17:52:00 +00:00
Stanislav Shwartsman
8be190d848 Implemented RDTSCP instruction 2005-08-05 12:47:33 +00:00