XOP: few instructions are still missing, coming soon
BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
So now the same single option will choose not only the CPUID flags but also VMX capabilities matching real HW machine.
Removed cpuid of core2_extreme_x9770 from the cpudb. I don't remember its VMX capabilities anyway.
There is another Penryn model in the cpudb - core2_penryn_t9600.
It was a real challenge to summarize all the highlights we have done in past half a year.
Hopefully it looks good and I didn't miss anything important.
32-bit CPU using Bochs binary compiled with x86-64 support.
The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
SMP emulation. New implementation uses dynamic CPU quantum value and takes
full advantage of the trace cache. Each emulated processor will execute
the whole trace before switching to the next processor.
* It is also safe to use large (up to 16 instructions) quantum values for
the SMP emulation now and improve performance even further.
The same merge also completely fixes SF bug :
[3312237] stepN command might be not working properly
Handlers chaining speedups are also supported with SMP emulation now.
with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
feature is enabled by default when configure with --enable-all-optimizations
option, to disable handlers chaining speedups configure with
--disable-handlers-chaining
Selecting CPU MODEL from .bochsrc automatically chooses real HW CPUID and also configures Bochs emulator to emulate this specific CPU including all its features only.
Supported CPUs to choose from:
core2_extreme_x9770
corei7_sandy_bridge_2600K
p4_prescott_celeron_336
The patch was posted in mailing list at Thu 6/16/2011.
Desription for CHANGES:
- Memory
- Added new configure option which enables RAM file backing for large guest
memory with a smaller amount host memory, without causing a panic when
host memory is exhausted (patch by Gary Cameron). To enable configure with
--enable-large-ramfile option.
