Stanislav Shwartsman
9929e6ed78
- updated FSF address
2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
aee488ea3a
Fixed dbg print
2009-01-13 22:54:49 +00:00
Stanislav Shwartsman
6451356d2b
make function to calculate allowed bits in cr4
2009-01-10 10:37:23 +00:00
Stanislav Shwartsman
836e9649d8
modify set cr0 functionality
2009-01-10 10:07:57 +00:00
Stanislav Shwartsman
4369152c70
- Make CS segment always writeable in real mode
2009-01-10 09:36:44 +00:00
Stanislav Shwartsman
7f65e6b9ed
change PANIC to ERROR
2008-12-13 18:40:39 +00:00
Stanislav Shwartsman
5174f9fe82
Fixed debian i386 image freeze
2008-12-08 20:01:26 +00:00
Stanislav Shwartsman
f9ce1171fe
rename crreg accessors
2008-12-06 10:21:55 +00:00
Stanislav Shwartsman
70e9f4c161
preparing to different way of handling MSR registers
2008-12-05 12:48:36 +00:00
Stanislav Shwartsman
fe0456d519
Remove extra ;;
2008-10-03 17:00:46 +00:00
Stanislav Shwartsman
fb71c07b15
Fixes for MONITOR/MWAIT - the feature is still EXPERIMENTAL ONLY !
2008-10-03 16:53:08 +00:00
Stanislav Shwartsman
bc381e51da
very small cleanups
2008-09-19 19:18:57 +00:00
Stanislav Shwartsman
a9c77eb75d
Try to optimize individual instructions after fetchdecode
2008-09-16 19:20:03 +00:00
Stanislav Shwartsman
23933d731c
Remove 4G limit optimization that didn't work quite well
2008-09-08 20:47:33 +00:00
Stanislav Shwartsman
f5ba90da55
Misaligned check small optimization
2008-09-08 15:45:57 +00:00
Stanislav Shwartsman
79eb5efffa
- Preliminary implementation of X86 IO breakpoints
2008-08-30 08:14:46 +00:00
Stanislav Shwartsman
db8445abde
Allow 8b BP in 32bit mode as well
2008-08-29 22:14:02 +00:00
Stanislav Shwartsman
991ae348cb
Clean invalidate_prefetch_q when not needed
2008-08-23 13:55:37 +00:00
Stanislav Shwartsman
460d91fc8c
Added missed #GP fault when writing invalid memtype to MTRR/PAT
2008-08-15 10:59:31 +00:00
Stanislav Shwartsman
dcb82ec4bf
Optimize TLB flush methods
2008-08-13 21:51:54 +00:00
Stanislav Shwartsman
24e0b53720
This more ellegant way to have debug info for BxError and not lose any performace
2008-08-09 19:18:09 +00:00
Stanislav Shwartsman
5dd02b26e3
Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before
2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
6398ebb1d4
First step of access bits cleanup and optimization - no perf gain yet
2008-08-03 19:53:09 +00:00
Stanislav Shwartsman
924c87e451
Delete unused code
2008-07-13 15:36:57 +00:00
Stanislav Shwartsman
709d74728d
Call #UD exception directly instead of UndefinedOpcode function - for future use
2008-07-13 15:35:10 +00:00
Stanislav Shwartsman
e9ec4fda48
Some chnages for future use
2008-07-13 10:44:34 +00:00
Stanislav Shwartsman
65275ffc02
Remove repeat speedups from 16-bit address size methods - they not gonna speed up anyway because of segment limit issue
2008-06-25 10:34:21 +00:00
Stanislav Shwartsman
c1f308d80d
Push error code if segment violation occurs when pushing arguments into a new stack
2008-06-25 02:28:31 +00:00
Stanislav Shwartsman
b65816a92d
Fixed problem in my morning checkin + some more changes
2008-06-23 15:58:22 +00:00
Stanislav Shwartsman
a6fda9a971
Instrumentation code updated, some PANIC messages fixed
2008-06-23 02:56:31 +00:00
Stanislav Shwartsman
fc6671a67b
Commented out assertion which doesn't work
2008-06-16 04:49:19 +00:00
Stanislav Shwartsman
9d1bc903d8
Fixed typo in MTRR, added assertions
2008-06-15 20:41:34 +00:00
Stanislav Shwartsman
a0e66d0e4c
fixed variable name
2008-06-14 16:55:45 +00:00
Stanislav Shwartsman
92568f7525
Faster 32-bit emulation wwith 64-bit enabled mode.
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~10% speedup byu optimization of 32-bit mem access
2008-06-12 19:14:40 +00:00
Stanislav Shwartsman
3d3dba7804
- Implemented GD bit in DR7 register
2008-06-02 19:50:40 +00:00
Stanislav Shwartsman
b7480b3e6f
- Fixed x86 data breakpoint match when breakpoint length is 8 bytes
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- FIxed x86 data breakpoint in paging disabled mode
2008-06-02 18:41:08 +00:00
Stanislav Shwartsman
d2ba79abdd
Removed PANIC in DqRq function
2008-05-31 21:17:02 +00:00
Stanislav Shwartsman
764756d74a
Handle reserved bits of CR8
2008-05-31 09:26:28 +00:00
Stanislav Shwartsman
d295371450
- Correctly handle segment a byte in BIG real mode
2008-05-26 21:46:39 +00:00
Stanislav Shwartsman
3619c0f6b4
Some changes to make x86-debugger feature working back
2008-05-23 17:49:46 +00:00
Stanislav Shwartsman
8118ba1a67
Fixed debug extensions exception priority
2008-05-19 19:59:29 +00:00
Stanislav Shwartsman
bef3450baa
Fixes to 64-bit mode
2008-05-11 20:46:11 +00:00
Stanislav Shwartsman
4a76bd2169
Fixed setting of reserved bits in CR3 register
2008-05-11 19:36:06 +00:00
Stanislav Shwartsman
ec1ff39a5f
Splitted memory access methods for 32 and 64-bit code.
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The 64-bit code got >10% speedup, the 32-bit code also got about 2% because laddr cacluation optimization
2008-05-10 18:10:53 +00:00
Stanislav Shwartsman
3634c6f892
Compress FPU tag word
2008-05-10 13:34:47 +00:00
Stanislav Shwartsman
6ebae41ad7
print physcial address with special format - preparations for 64-bit physical address emu
2008-05-09 22:33:37 +00:00
Stanislav Shwartsman
80c9b5fcbe
Compilation error fixed
2008-05-09 08:28:00 +00:00
Stanislav Shwartsman
eedf26627f
Fixes in CMPXHG8B instruction - slight speedup and correct #AC check
2008-05-05 21:48:07 +00:00
Stanislav Shwartsman
64a80c8a2d
- Added canonical check for SYSENTER MSRs in WRMSR
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- Fixed LLDT and LTR instructions in 64-bit mode
- Fixed error code for not 64-bit CS in interrupt from long mode
2008-05-04 21:25:16 +00:00
Stanislav Shwartsman
50c9674d2e
Small optimization in memory access functions
2008-05-03 17:33:30 +00:00
Stanislav Shwartsman
06c6ac0060
- Fixed effective address wrap in 64-bit mode with 32-bit address size
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- Fixed SMSW instruction in 32-bit and 64-bit modes
2008-04-28 18:18:08 +00:00
Stanislav Shwartsman
67e534832b
Remove from CPU reference to MEM object - it is only one and could be static
2008-04-27 19:49:02 +00:00
Stanislav Shwartsman
9047c9be96
Support for reserved bits checking in paging
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Check for page is in DTLB before invalidating by INVLPG
2008-04-25 20:08:23 +00:00
Stanislav Shwartsman
a647c7e551
Check for old TSS limits in task switching logic
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MSR_GSKERNELBASE should be canonical - added WRMSR check
2008-04-25 11:39:51 +00:00
Stanislav Shwartsman
24f1507fa9
- sysenter/exit should be supported in v8086 mode as well
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- fixed missed CS.LIMIT check in all far calls/jmps in real/v8086 mode
2008-04-20 21:44:13 +00:00
Stanislav Shwartsman
280617288c
Mode change in SYSENTER/EXIT/CALL/RET could happen only when already in long mode
2008-04-20 18:17:14 +00:00
Stanislav Shwartsman
a91ef4e31b
Ignore CS.L bit when EFER.LMA is not set
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Add potentially missed CPU mode change in SYSCALL/RET/ENTER/EXIT
2008-04-20 18:10:32 +00:00
Stanislav Shwartsman
d9bf2b8453
Small emulation speed optimization
2008-04-19 22:29:44 +00:00
Stanislav Shwartsman
15e9dca062
- support 64-bit write to MSR_TSC using WRMSR instruction
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- fixed save/restore param type for async_event
- fixed setting of reserved bits in upper part of CR4 in 64-bit mode
2008-04-18 18:32:40 +00:00
Stanislav Shwartsman
892fa99c6f
- prefetch hint should be NOP when use in register mode
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- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
67f02bfa12
Add debugger callback
2008-04-15 21:29:18 +00:00
Stanislav Shwartsman
fab4042cad
SYSENTER/SYSEXIT in long mode
2008-04-15 14:41:50 +00:00
Stanislav Shwartsman
a851cfd8f0
Re-implemented modebp debugger function in simple and more clean way
2008-04-07 19:59:53 +00:00
Stanislav Shwartsman
fea49bb270
Fixed linear address wrap in legacy (not long64) mode
2008-04-07 18:39:17 +00:00
Stanislav Shwartsman
5826e2843a
Inline pop/push functions
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Store only single byte of opcode in b1() - speedup shift instructions
Code cleanups
2008-04-05 17:51:55 +00:00
Stanislav Shwartsman
41fe0b3ebb
Fix code duplication
2008-04-03 18:59:10 +00:00
Stanislav Shwartsman
e91409704f
Convert EFER to val32 register, similar to other control registers
2008-03-31 20:56:27 +00:00
Stanislav Shwartsman
a22160959b
HLT callback to Bochs internal debugger
2008-03-23 21:39:01 +00:00
Stanislav Shwartsman
167c7075fb
Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code
2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
a459a64f3e
whispace, tab2space, indent, dos2unix and other cleanups
2008-02-15 22:05:43 +00:00
Stanislav Shwartsman
cdcd7522aa
Added RIP to the GPR register file as lst register
...
This allowed to optimize (read - remove) two more BxResolve methods in 64-bit mode
+ Some white space cleanup
2008-02-15 19:03:54 +00:00
Stanislav Shwartsman
8615022962
Added first stubs for XSAVE/XRESTOR implementation
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Disassemble XSAVE/XRSTOR instructions (4 instructions)
Update CHANGES - a bit speculatively
2008-02-12 22:41:39 +00:00
Stanislav Shwartsman
8d7410a852
Canonical check have higher priority than #AC check
2008-02-11 20:52:10 +00:00
Stanislav Shwartsman
965568ea88
cleanups
2008-02-07 18:28:50 +00:00
Stanislav Shwartsman
a2897933a3
white space cleanup
2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
032b13047c
Minor fix in cpu reset, bug sometimes caused to run on garbage memory after software reset. Some small debug messages fixes
2008-02-01 13:25:23 +00:00
Stanislav Shwartsman
d18b90484f
Added instr callbacks for sysenter/sysexit/syscall/sysret
2008-01-18 08:57:35 +00:00
Stanislav Shwartsman
e287dcd91a
correctly implement CLFLUSH protection/paging checks + add instrumentation callback
2008-01-16 22:56:17 +00:00
Stanislav Shwartsman
d9984bb3a1
Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup !
2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
838fb2a048
Fixing V2008 warnings - they found a bug in sse_pfp.cc !
2007-12-23 17:21:28 +00:00
Stanislav Shwartsman
5d4e32b8da
Avoid pointer params for every read_virtual_* except 16-byte SSE and 10-byte x87 reads
2007-12-20 20:58:38 +00:00
Stanislav Shwartsman
b516589e4e
Changes in write_virtual_* and pop_* functions -> avoid moving parameteres by pointer
2007-12-20 18:29:42 +00:00
Stanislav Shwartsman
46366b5064
Speedup simulation by eliminating CPL==3 check from read/write_virtual* functions
2007-12-16 21:03:46 +00:00
Stanislav Shwartsman
d9a59c7a1f
Added ability to merge traces cross JCC branch instructions
...
Makes traces longer -> emulation faster in average
2007-12-14 20:41:09 +00:00
Stanislav Shwartsman
db69a25c36
Trace cache instrumentation methods
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Next step will be tracing cross non-taken branches
2007-12-14 11:27:44 +00:00
Stanislav Shwartsman
48d815427c
According to AMD docs INVLD/WBINVLD instructions not required to flush TLBs
2007-12-14 10:15:12 +00:00
Stanislav Shwartsman
85d10e4f72
Added MWAIT callback
2007-12-13 21:41:32 +00:00
Stanislav Shwartsman
91e0db63c4
no need to invalidate prefetch queue for RDMSR/WRMSR
2007-12-03 21:43:14 +00:00
Stanislav Shwartsman
c58e95f611
Make hw breakpoint match check a function - normally it should be called from read/write_virtual as well
2007-12-03 20:49:24 +00:00
Stanislav Shwartsman
8cfd17202a
some simple SSE code optimizations
2007-11-27 22:12:45 +00:00
Stanislav Shwartsman
48650a70b4
Optimized alignment check
2007-11-20 21:22:03 +00:00
Stanislav Shwartsman
e1496bb9e0
Small optimization
2007-11-18 18:40:38 +00:00
Stanislav Shwartsman
d9e58bd598
split11b on opcode tables level - split almost eevery splittable instruction
...
will be continued
2007-11-17 12:44:10 +00:00
Stanislav Shwartsman
24e1936fbb
Fixed compilation warning when compiling with no x86-64
2007-11-09 12:06:34 +00:00
Stanislav Shwartsman
5a172541e2
Small cleanup
2007-11-01 20:43:53 +00:00
Stanislav Shwartsman
e137560b14
Complete MONITOR/MWAIT implemntation (including monitoring of memory range)
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Fixed PANIC in read/write Cr/Dr - should #UD with unkown register used
2007-11-01 18:03:48 +00:00
Stanislav Shwartsman
4ec7f5df39
Optimize access to IP (16 bit) - made IP register similar to GPR
2007-10-18 22:44:39 +00:00
Stanislav Shwartsman
082eb05b6b
First step to fully configurable CPUID
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- put CPUID functions data into array, in future we could load this array from configure file
- cpuid initialize function is more flexible now but still reuire some work
2007-10-12 19:30:51 +00:00
Stanislav Shwartsman
8adbbcf17c
Started first implementation of MONITOR/MWAIT
2007-10-11 21:29:01 +00:00
Stanislav Shwartsman
f6ed95785f
added cpu state param - for future use and for dbg info
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started to move debugger to info bx_param interface -> info sse and info mmx commands modified
2007-10-11 18:12:00 +00:00
Stanislav Shwartsman
82b7eaabd5
CLFLUSH do not fault when checking execute only segment
2007-10-10 21:48:46 +00:00
Stanislav Shwartsman
071c5c1a26
A lot of changes but everything is really trivial.
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Make save/restore default feature, the configure option for save/restore removed from configure script and save/restore made available forever. All code now assume it is exists. Bochs save/restore tree previosly called "save_restore" renamed to "bochs" tree and it will be havily used everywhere, starting from save/restore and ending by various bochs debugger functions. I am going to rework debugger code to get rid of debug CPU access functions and use this "bochs" param tree instead
2007-09-28 19:52:08 +00:00
Stanislav Shwartsman
e812f81e7b
Fixes in zero upper ECX
2007-09-25 16:11:32 +00:00
Stanislav Shwartsman
91e6ca8d5c
Implemented MTRR support
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Fixes in #PF exception priority
2007-09-20 17:33:35 +00:00
Stanislav Shwartsman
70f513b07b
Make efer control MSR separate register
2007-09-10 20:47:08 +00:00
Stanislav Shwartsman
895891b673
Implemented #AC check under configure option
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Fixes in misaligned SSE support
2007-07-31 20:25:52 +00:00
Stanislav Shwartsman
38d1f39c77
Converted CR0 bits to one register similar to CR4 - a bit slower but helps with other features implemntation
2007-07-09 15:16:14 +00:00
Stanislav Shwartsman
7c6c2bb520
Removed PANIC message
2007-06-08 09:25:30 +00:00
Stanislav Shwartsman
65a99eb736
Change BX_ERROR to BX_DEBUG
2007-04-25 20:14:15 +00:00
Stanislav Shwartsman
6c139a9c8c
Define LIN and PHY address size in config.h
2007-04-14 10:05:30 +00:00
Stanislav Shwartsman
d3252fbc1c
Removed unneeded invalidate_prefetch_q from RDMSR instruction
2007-02-23 22:08:43 +00:00
Stanislav Shwartsman
c24627c00f
Implemented CLFLUSH instruction
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Set of minor fixes for correctness
2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
6c63e84d23
Fixed CR3 masking in long mode
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Added PANIC assertion of 32-bit physical address in PAE mode
cleanup
2006-10-04 19:08:40 +00:00
Stanislav Shwartsman
02c2fc9e89
Fixed priveledge level checks
2006-09-10 16:56:55 +00:00
Stanislav Shwartsman
fdac9efa9b
Fixed ton of code duplication.
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Do not save/restore XMM8-XMM15 not in 64-bit mode
2006-08-31 18:18:17 +00:00
Stanislav Shwartsman
65082e4a4f
Handle granularity field for LDT
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Next step - fix code duplication with TSS
2006-08-25 19:56:03 +00:00
Stanislav Shwartsman
3ce7764fce
Fixes in 64-bit decoding
2006-08-11 17:23:36 +00:00
Stanislav Shwartsman
45353d5e6f
Fixed DR registers handling in x86-64 mode
2006-06-26 21:07:44 +00:00
Stanislav Shwartsman
9269288319
Fix SR macros mis-use. Need to add assertion into bxlist_c and check that it has no 2 params with same name inside !
2006-06-14 16:44:33 +00:00
Stanislav Shwartsman
49d7b4614f
Fixed another bug generator - duplication between descriptor type field and four descriptor cache bits
2006-06-12 16:58:27 +00:00
Stanislav Shwartsman
308521e7ce
Fixes in SYSCALL/SYSRET instructions
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Use parse_selector to avoid code duplication
2006-06-11 21:37:22 +00:00
Stanislav Shwartsman
6c3420a18b
Add debug prints before any #GP excepion which only possible to be generated
2006-06-09 22:29:07 +00:00
Stanislav Shwartsman
8b55085c76
Merge tss286 and tss386 segment descriptor cache fields to one structure
2006-05-21 20:41:48 +00:00
Stanislav Shwartsman
f4c7b4074e
Support for x86-64 in x86 debugger (DR0-DR7)
2006-05-13 12:49:45 +00:00
Stanislav Shwartsman
9a32d0e98f
Optimize debug registers handling
2006-05-13 12:29:12 +00:00
Stanislav Shwartsman
63dc4d4e10
Fixed CR4 GP(0) condition (patch by no_mayl in mailing list)
2006-04-23 16:11:16 +00:00
Stanislav Shwartsman
d972e4a4b7
Fixed CR3 restore in RSM instruction
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Added HALT state indication (actually make existant one working for single CPU)
2006-04-10 19:05:21 +00:00
Stanislav Shwartsman
45f30f0a4c
some code written to enter CPU to shutdown state.
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finally the shutdown handling should be done exactly as in VmWare - the GUI should ask user if the CPU should reset and go to HLT/IF=0 if user choosed to stay in shutdown mode.
CPU configure option reset-on-triple-failt should be extended to shutdown-reset=0|1
small code cleanups and fixes
2006-04-07 20:47:32 +00:00
Stanislav Shwartsman
f8c3968d42
Changes list made after CVS service crash:
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- Fixed critical bug in CPU code added with one of the prev commits
- Disasm support for SSE4
- Rename PNI->SSE3 everywhere in the code
- Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
- Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
- Fixed ENTER and LEAVE instructions in x86-64 mode
- Added ability to turn ON instruction trace, only GUI support is missed.
Instruction trace could be enabled if Bochs was compiled with disasm
- More changes Bit32u -> bx_phy_address
- Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
- Small code cleanup
- Update CHANGES and user docs
2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
da3d26d7f4
Preliminary implemntation of SMM save statei
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Fixed fetchModeMask for load32bitOsStack
2006-03-27 18:02:07 +00:00
Stanislav Shwartsman
f347ab97bf
Fixed CALL/JMP far through call gate 64
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Decode SWAPGS and RDTSCP instructions
Indent changes in fetchdecode
2006-03-22 20:47:11 +00:00
Stanislav Shwartsman
a64b16391d
Remove unused vars
2006-03-15 17:57:11 +00:00
Stanislav Shwartsman
e85a90a720
Remove cpu.h -> devices.cc dependancy, kill_bochs_request moved from CPU to bx_pc_system
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Small Icache simplification and speedup
2006-03-14 18:11:22 +00:00
Stanislav Shwartsman
7b6c2587a9
Now devices could be compiled separatelly from CPU
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Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
324d75e749
Fix another broking change
2006-03-04 09:22:55 +00:00
Stanislav Shwartsman
5fad793989
move local apic handling to the access_linear function for the memory class.
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speedup the whole simulation by 2% !
2006-03-01 22:32:24 +00:00
Stanislav Shwartsman
a527b2cfca
first smm - implement cpu state when switching to SMM
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smm coming soon
fixed code duplication in init.cc
2006-02-28 19:50:08 +00:00
Stanislav Shwartsman
55ceecf79b
Small optimization in icache page-write-stamp
2006-02-28 17:47:33 +00:00
Stanislav Shwartsman
024ce249bf
Define SMM mode for future implementation.
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I would like all next commits be aware of SMM mode.
It can't be implemented right now (too many questions w/o answers) but it will be done till next major release definitelly.
2006-02-14 19:00:08 +00:00
Stanislav Shwartsman
9b451f43e2
Save/restore RIP/RSP only on FAULT type exceptions, not on traps
2006-02-11 09:08:02 +00:00
Stanislav Shwartsman
9a15f59e05
Fixed bug in SYSRET legacy mode
2006-02-02 17:55:48 +00:00
Stanislav Shwartsman
9df8079206
Write to MSR_TSC implemented (patch by Bryce)
2006-01-21 12:06:03 +00:00
Stanislav Shwartsman
7bf51e48db
Print FS_MSR_BASE and GS_MSR_BASE to debug registers dump (requested in bug report [ 1406387 ] JMP instruction should display absolute address)
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Fixed fetch mode mask initialization (bug report 1400027 Boundary instruction cache error for uninitialized memory)
For safety only - everytime when changing CS register update fetch mode mask.
Actually it need to be updated everytime when there is a chance for execute mode change or 16/32 bit mode change.
2006-01-16 19:22:28 +00:00
Stanislav Shwartsman
a74b63eb3d
Allow writing PCE to CR4
2006-01-13 11:11:29 +00:00
Stanislav Shwartsman
393a653fb4
Fix typo
2006-01-05 21:40:07 +00:00
Stanislav Shwartsman
70cc5a7fb0
Fix incorrect commit
2005-12-12 19:54:48 +00:00
Stanislav Shwartsman
f863d1e902
Generate #GP exception instead of #TS when TSS selector points to bad TSS
2005-12-12 19:44:06 +00:00
Stanislav Shwartsman
fe02ecab65
Do not flood log with WBINVD/INVD messages
2005-11-27 18:36:19 +00:00
Stanislav Shwartsman
8c91790680
Redefine registers accessors in cpu.h
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Change BxSupportPAE and BxSupportGlobalPages macros to Bochs style names
Set bx_cpu_id in BX_CPU_C constructor (safe way)
Backup cpu-level check for paging features at compile time (already checked in configure)
Some warnings and indent fixes
speed up get_segment_base method for x86-64 case
2005-11-26 21:36:51 +00:00
Stanislav Shwartsman
9314752bb1
Rewritten task_switch mechnism according to AMD docs
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This should fix the #SF bug report
736279 Jump to Task
2005-11-21 21:10:59 +00:00
Stanislav Shwartsman
cd2a9f317d
Do not PANIC when HLT with IF=0, only BX_INFO
2005-11-04 15:15:02 +00:00
Stanislav Shwartsman
ab81296e33
Update CHANGES/TODO
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Change BX_INFO to BX_DEBUG in read CR4 function
2005-10-23 21:11:32 +00:00
Stanislav Shwartsman
64ba97210b
INVD/WBINVD should flush caches and TLB
2005-10-18 18:07:52 +00:00
Stanislav Shwartsman
670395f1be
VME support - beta #1
2005-10-17 13:06:09 +00:00
Stanislav Shwartsman
e83c77db49
Preparing to VME implementation
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DO NOT ENABLE VME option until the implementation will be completed !
2005-10-16 23:13:19 +00:00
Stanislav Shwartsman
469358aaf9
Move SHOW_IPS action to bx_gui object, may be some GUI will be able to print IPS online in the simulation window status bar ...
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Small code cleanup
2005-10-13 16:22:21 +00:00
Stanislav Shwartsman
39fc11c5da
Fix compilation error
2005-10-09 18:32:36 +00:00
Stanislav Shwartsman
7869ab425f
LTR should #GP when loading NULL selector
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fixed check for SYSENTER/SYSEXIT instructions
according to new Intel references
2005-10-01 07:47:00 +00:00
Stanislav Shwartsman
8c783bc329
Fixed cpu_mode corruption in x86-64 mode
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Removed all potentially unsafe and duplicated code in setFLAGS methods to avoid such kind of problems in future
2005-09-29 17:32:32 +00:00
Stanislav Shwartsman
6096698393
Fixed CLTS and HLT GP0 check
2005-09-14 20:01:42 +00:00
Stanislav Shwartsman
8be190d848
Implemented RDTSCP instruction
2005-08-05 12:47:33 +00:00
Stanislav Shwartsman
954aae3f99
Speedup push/pop operations, they actually not needed to do can_push/can_pop checkes, the same checkes already done in read/write_virtial methods
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Split push_seg_reg methods according to op size
2005-07-31 17:57:27 +00:00
Stanislav Shwartsman
5da36b7d3d
Fixed code duplication, added canonical address checking for RETF in long mode
2005-07-29 06:29:57 +00:00
Stanislav Shwartsman
4638f09b24
Added BX_INSTR_HLT instrumentation callback
2005-07-07 18:40:35 +00:00
Stanislav Shwartsman
3d2e2162f3
Code indent, no functionality changes
2005-07-01 14:06:02 +00:00
Stanislav Shwartsman
015ad92958
Added SMP status to TODO file
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Removed abusive BX_INFO from WBINVD instruction
The PREFETCHW (3DNow!) instruction should not #UD in x86-64 even on Intel w/o 3DNow!
2005-05-27 01:53:38 +00:00
Stanislav Shwartsman
6c318bd047
SFENCE/MFENCE/LFENCE methods not defined in CPU class and they NOP in fetchdecode.cc
2005-05-18 05:05:40 +00:00
Kevin Lawton
f829c9cf93
Typo in CR8 handling in MOV_CqRq/MOV_RqCq had a typo. A switch
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target of 7 was used instead of 8.
2005-05-17 22:22:35 +00:00
Stanislav Shwartsman
494af8b1f3
Fixed segmentation fault for 2CPU cfg
2005-04-26 19:19:58 +00:00
Stanislav Shwartsman
501cca67c2
Fix compilation err
2005-04-18 17:41:15 +00:00
Stanislav Shwartsman
8482511af3
Fix compilation errors
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Add BX_INFO for writing to TSC_MSR (not implemented message)
2005-04-18 17:21:34 +00:00
Stanislav Shwartsman
0f7f728e86
Added debug messages for interrupt function in long mode
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Added mode switch debug prints
2005-03-30 20:53:04 +00:00
Stanislav Shwartsman
e6e9dd3825
Extend Bochs instrumentation
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Compatability fixes
2005-03-17 20:50:57 +00:00
Stanislav Shwartsman
6e53a54907
Extend cpu_mode for :
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#define BX_MODE_IA32_REAL 0x0 // CR0.PE=0
#define BX_MODE_IA32_PROTECTED 0x1 // CR0.PE=1, EFLAGS.VM=0
#define BX_MODE_IA32_V8086 0x2 // CR0.PE=1, EFLAGS.VM=1
#define BX_MODE_LONG_COMPAT 0x3 // EFER.LMA = 0, EFER.LME = 1
#define BX_MODE_LONG_64 0x4 // EFER.LMA = 1, EFER.LME = 1
2005-03-15 19:00:04 +00:00
Stanislav Shwartsman
c30e89289b
Fixed R/O pages access in CPL=3 (TLB accessBits bug)
2005-03-03 20:24:52 +00:00
Stanislav Shwartsman
c583a6f9cf
move segments and descriptors definitions and macroses for new descriptor.h
2005-02-27 17:41:45 +00:00
Stanislav Shwartsman
6e773a652a
Fix SYSENTER/SYSEXIT instructions
2005-02-26 12:00:22 +00:00
Stanislav Shwartsman
830ca51b91
Merge patches:
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1149720 critical - fix x86-64 SYSCALL RFLAGS masking
1149758 wrmsr efer fix
2005-02-23 18:00:07 +00:00
Stanislav Shwartsman
2bfc842c09
CPU fixes by Kevin Lawton
2005-02-16 21:27:21 +00:00
Stanislav Shwartsman
5701f62a42
Fix compiler warnings with -wall
2005-02-03 18:43:23 +00:00
Stanislav Shwartsman
d27e81bdac
-in case of --enable-ignore-bad-msr enabled read ignored MSRs as zeRo
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- enabled #DE and #TSD and #MCE bits in CR4 register, previosly setting
of one of these bits generated #GP(0) (Stanislav, Volker Ruppert)
2005-02-03 18:25:10 +00:00
Stanislav Shwartsman
7eb2f0aa3e
Enable TSD in CR4 (RDTSC instruction is already implemented so it has no problem to enable TSD for CPU LEVEL >=5)
2005-01-23 21:13:49 +00:00
Stanislav Shwartsman
3cd646004f
Fixed bug "1101168 APIC base address change"
2005-01-13 19:03:40 +00:00
Volker Ruppert
48ebc288c6
- MCE is supported on Pentium or higher (exception 18 never appears in Bochs)
2005-01-09 08:14:15 +00:00
Stanislav Shwartsman
5955549a8d
Fixed bug report [ #879050 ]
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Bochs reports enabled APIC without support
2004-12-14 20:41:55 +00:00
Stanislav Shwartsman
730b8c0243
Fix this pointers in the code
2004-11-14 21:25:42 +00:00
Stanislav Shwartsman
1a6656ce91
Fixed compilation warnings (g++, -Wall)
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Improve speed and precision of FPATAN FPU instruction
2004-11-04 22:41:24 +00:00
Stanislav Shwartsman
f06c8b6b95
EIP > CS.limit should not be a problem
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Manual says that GP(0) shouldd be generated in this case ALWAYS
Fixed instructions PANIC messages to ERROR for this case
And ... do not leave PANIC messages w/o taking care that user could push CONTINUE button and program should know to continue after the PANIC code line. Mainly in rerurn instructions were several problems ...
2004-11-02 16:10:02 +00:00
Stanislav Shwartsman
80ee150d83
Imlemented CR8 register for X86-64 mode
2004-10-13 20:58:16 +00:00
Stanislav Shwartsman
4988a098f5
Small optimizations
2004-10-03 21:52:10 +00:00
Stanislav Shwartsman
040be015d8
1. Added required GP(0) exception when setting conficting flags in CR0
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2. APIC disabled compilation error fixed
2004-09-21 20:19:19 +00:00
Stanislav Shwartsman
5c5b556f24
Merge softfloat-fpu-implementation_ver4_branch branch
2004-06-18 14:11:11 +00:00
Stanislav Shwartsman
e6991f043f
pply patch
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[ 924428 ] ET bit mismatch between CR0 and MSW
2004-06-03 17:57:29 +00:00
Stanislav Shwartsman
3274e0dd12
Commit patch
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[ 950905 ] Do not PANIC on rare, bad input from user-mode
by h.johansson
with little changes and fixes
2004-05-10 21:05:51 +00:00
Stanislav Shwartsman
cdb68ff8c8
Reverting back the changes in data_xfer16.cc
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Add/Fix bx_info messages in proc_ctrl.cc
2003-11-13 21:57:13 +00:00
Stanislav Shwartsman
d51aece0c1
Change BX_PANIC messages to BX_INFO when behaviour is accepted with Intel/AMD docs.
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Instructions MOV_CxRx and MOV_RxCx are not supported in v8086 mode according to Intel manuals.
Also these instructions are treated as register-to-register regardless to MODRM byte fields (according to AMD manuals)
Also commit fix for MOV_EwSw by Kevin
2003-11-13 21:17:31 +00:00
Stanislav Shwartsman
ac20b6405a
- FXSAVE/FXRSTOR instructions should be available in P6 mode
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- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
789db2603e
Added P4 support to CPUID instruction
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Extracted CPUIS instructions to separate file
2003-09-26 15:32:41 +00:00
Stanislav Shwartsman
7f570b0150
Added PNI new streaming extensions instructions
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PNI could be enabled by setting BX_SUPPORT_PNI in config.h
After the feature will be fully validation I'll also add configure option.
The implemntation is ~complete. I've missed only three FPU new opcodes of FUSTTP instruction and MONITOR/WAIT instructions.
Enjoy ! ;)
2003-08-29 21:20:52 +00:00
Stanislav Shwartsman
549eb70324
Committed CPU fixes from Vitaly Vorobyov:
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[x] fixed bug in int01 (opcode 0xF1) emulation
[x] fixed bug in x86 debugger with dr0-dr3 registers
Committed disassembler bugfix from Dirk Thierbach:
[x] fixed bug in relative addresses in Jmp, Jcc, Call and so on
2003-08-03 16:44:53 +00:00