mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
10,221 Commits 11 Branches 185 Tags 48 MiB
46e36b463b
Commit Graph

51 Commits

Author SHA1 Message Date
Stanislav Shwartsman
37a3a76cbb optimize old disasm code 2013-10-07 19:23:19 +00:00
Stanislav Shwartsman
cb0eee9456 disasm fixes 2013-10-07 19:02:53 +00:00
Stanislav Shwartsman
e55611df21 disasm fixes 2013-10-06 19:04:52 +00:00
Stanislav Shwartsman
add8eea761 disasm bug fixes 2013-10-06 18:37:56 +00:00
Stanislav Shwartsman
25f99f76c3 remove test registers from disasm as well 2013-08-23 05:54:51 +00:00
Stanislav Shwartsman
2638c1136a Add RDRAND/RDSEED instructions support (+ disasm) 
Of course no true random numbers will be generated - use standard "C" rand() function as stub.
In future it will be possible to improve (using another random generator) or even use real rdrand/rdseed intrinsics
 2012-10-09 15:16:48 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
9be8552b80 - Implemented VM Functions support and EPTP-Switching VM Functions 
- Added VMEXIT conditions for INVPCID instruction

Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
 2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
1f5e036695 lzcnt/tzcnt bmi instructions implemented 2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
8962cfddde re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc 2011-08-12 18:04:56 +00:00
Volker Ruppert
c78026a9a2 - deleted executable properties from source files 2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
00981cd7a6 Adding Id and Rev property to all files 2011-02-24 22:05:47 +00:00
Stanislav Shwartsman
dc72673bb3 Fixed arpl disasm 2010-10-11 15:33:11 +00:00
Stanislav Shwartsman
7f7c249934 disasm and some cpuid code according to recently published AVX_319433-007.pdf document 2010-07-22 15:12:08 +00:00
Stanislav Shwartsman
2dbe559ad9 simpler disasm tables 2010-05-23 20:05:14 +00:00
Stanislav Shwartsman
8d8d1590f5 fetchdecide rework for AVX (0xF3 SSE prefix encoded as 2 in VEX) 2010-05-23 19:17:41 +00:00
Stanislav Shwartsman
c841eaa953 fixes and cleanups in disasm and decoder 2010-02-09 19:44:25 +00:00
Stanislav Shwartsman
8330354f67 split disasm to more files 2010-02-08 15:11:58 +00:00
Stanislav Shwartsman
7aaa32f337 fix disasm bugf 2010-02-02 13:06:13 +00:00
Stanislav Shwartsman
eae084920a optimized decode tables 2010-01-31 09:45:27 +00:00
Stanislav Shwartsman
b5d1677848 GETSC instruction disasm 2010-01-11 21:27:59 +00:00
Stanislav Shwartsman
db8ecc535e added mclmulqdq disasm 2009-12-17 09:13:35 +00:00
Stanislav Shwartsman
7254ea36a1 copyright fixes + small optimization 2009-10-14 20:45:29 +00:00
Stanislav Shwartsman
87103c2437 Support for disasm of MOVBE Intel Atom(R) instruction 2008-08-11 17:55:57 +00:00
Stanislav Shwartsman
a85dfc7617 Added disasm for AES instructions 2008-05-25 15:42:26 +00:00
Stanislav Shwartsman
64f2489afb Correctly implement opcode group G11 i.e. instructions C6 and C7 should @UD when modrm nnn field != 0 (1st instr in the group 2008-04-24 21:52:28 +00:00
Stanislav Shwartsman
0609d7e7ce Handle undocumented FPU opcodes 2008-04-21 14:17:48 +00:00
Stanislav Shwartsman
405fcfd75d Reorganize 3-byte opcode tables - bigger tables but easier to maintain them 2008-02-29 03:02:03 +00:00
Stanislav Shwartsman
8615022962 Added first stubs for XSAVE/XRESTOR implementation 
Disassemble XSAVE/XRSTOR instructions (4 instructions)
Update CHANGES - a bit speculatively
 2008-02-12 22:41:39 +00:00
Stanislav Shwartsman
eebd96e2d7 another whitespace cleanup by Sebastien 2008-02-05 22:33:35 +00:00
Stanislav Shwartsman
033150c7e6 According to AMD docs opcodes 0f 19...0f 1f are multibyte NOP 2007-11-17 16:19:14 +00:00
Stanislav Shwartsman
de72d9141f Disasm updates (bugfixes) + disasm of all SSE4_2 instructions 2007-10-01 19:57:46 +00:00
Stanislav Shwartsman
0dc4badfbb Added SSE4A and SSE4_2 to disassembler 
Implemented POPCNT instruction
 2007-09-19 19:38:10 +00:00
Stanislav Shwartsman
b64fc08c54 implement prefetch hint opcodes 2007-08-23 16:47:51 +00:00
Stanislav Shwartsman
5189cfbf10 SSE4 support 2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
2d47748f52 Added instruction set field for opcodes table + few bugfixes 2007-04-02 10:47:48 +00:00
Stanislav Shwartsman
4bb19c2dc3 Fixed deciding and disasm of CALL in 64-bit mode (no 16-bit calls allowed) 2007-03-28 21:20:09 +00:00
Stanislav Shwartsman
4f166369a6 Fixes for VMX disasm 2007-03-23 22:07:49 +00:00
Stanislav Shwartsman
ef542b3790 Learn to decode and disassemble VMX opcodes 
No fetchdecode support but everything is ready
 2007-03-23 14:35:50 +00:00
Stanislav Shwartsman
f39abc9b65 Fix for bug 
[ 1513544 ] disasm of 0xec (in AL,DX) returns ilen of 2 instead of 1
 2006-06-27 19:26:53 +00:00
Stanislav Shwartsman
caee480547 Fixed DR registers disasm 2006-06-26 21:06:26 +00:00
Stanislav Shwartsman
4d1a609c8c BSWAP 16-bit mode not exists, correctly disasm this case 2006-05-07 19:12:56 +00:00
Stanislav Shwartsman
c7773adac4 Norhing changed in funtionality, just make the file significantly smaler by removing extra spaces 2006-04-05 20:54:30 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash: 
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
 2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
6b2ab6aa92 Fixed movhps/movlps instructions disasm 2006-02-17 17:13:58 +00:00
Stanislav Shwartsman
2dc81b172a Fixed several disasm bugs 2006-02-17 13:33:05 +00:00
Stanislav Shwartsman
24d4de03a1 - Fixed bug with missed ES segment override prefix 
- Correctly disassemble x86-64 opcodes

	Ia_cvttsd2si_Gq_Wsd
	Ia_cvttss2si_Gq_Wss
	Ia_cvtsd2si_Gq_Wsd
	Ia_cvtss2si_Gq_Wss
	Ia_movq_Pq_Eq
	Ia_movq_Vdq_Eq
	Ia_movq_Eq_Pq
	Ia_movq_Eq_Vq

- Correctly disassemble Intel SSE3 opcodes (not supported by Bochs)
	Ia_monitor
	Ia_mwait
 2006-01-31 17:42:31 +00:00
Stanislav Shwartsman
934f552ea3 Fix disassembly 2006-01-30 17:39:17 +00:00