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439 Commits

Author SHA1 Message Date
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
b891789c3d implemented (experimental) TSC Adjust MSR 2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
dd3849b9e0 extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation 2020-05-19 16:01:23 +00:00
Stanislav Shwartsman
7a5fef764b fix for effcetive TSC compute when TSC multiplier is enabled 2020-05-17 18:39:52 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
276482e67d fix set_PKRU method 2019-12-04 18:52:00 +00:00
Stanislav Shwartsman
27e23ad1eb give priority for VMX induced #UD in INVPCID and RDTSCP instructions over all other exeptions that could be generated there 2019-10-24 19:49:25 +00:00
Stanislav Shwartsman
85780d939a extract MONITOR/MWAIT stuff to separate trsnlation unit 2019-05-25 18:32:17 +00:00
Stanislav Shwartsman
3995dc13aa fixed compilation of CLZERO pn cpu-level<6 2018-08-26 18:11:10 +00:00
Stanislav Shwartsman
fd15b61d94 keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM 2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
5439647254 small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in 2017-10-19 21:27:25 +00:00
Stanislav Shwartsman
bde8a1f69d fixed ifdef typo 2017-06-01 07:48:54 +00:00
Stanislav Shwartsman
3d51439090 fixed compilation err for CPU_LEVEL=5 2017-04-13 05:33:29 +00:00
Stanislav Shwartsman
a51eb1cc39 added more debug info for TLB through param tree, update year in the (c) 2017-03-31 07:34:08 +00:00
Stanislav Shwartsman
c9c3672509 allow monitor to UC memory type but not MONITORX 2017-03-31 07:00:36 +00:00
Stanislav Shwartsman
a673612784 fixed permission checks performed by CLFLUSH/CLFLUSHOPT/MONITOR* instructions 2017-03-28 18:52:53 +00:00
Stanislav Shwartsman
2b79061127 Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model 2017-03-26 19:14:15 +00:00
Stanislav Shwartsman
411ea954b4 implemented CLZERO instruction from AMD Ryzen CPU 2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
10eb193e01 step 1 of rewrite Bochs decoder: legacy decoder tables done. TODO: avx/evex decoder tables, merge decoder and disasm together 2017-01-10 20:15:17 +00:00
Stanislav Shwartsman
7a34f00f99 extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all 2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
e4832af5ab clean pkeys when not enabled to avoid side-effects 2016-03-19 21:15:56 +00:00
Stanislav Shwartsman
5b481fe34d correctly set up pkeys when enabling through cr4 2016-03-19 19:48:38 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
8d13b61319 implemented TSC Scaling VMX feature according to timestamp-counter for virtualization whitepaper published by Intel 2015-09-30 18:44:01 +00:00
Stanislav Shwartsman
c44cb6ed81 more cases applicable for BX_TLB_ENTRY_OF 2015-09-22 20:10:22 +00:00
Stanislav Shwartsman
da39e57196 comment fixes 2015-09-08 19:14:58 +00:00
Stanislav Shwartsman
f6af0443bb small optimization and elimination of several defines from cpu.h - replace by inline functions and const variables 2015-07-13 20:24:14 +00:00
Stanislav Shwartsman
b468316250 re-style old resolve macros after resolve function inlining 2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
9f18573740 Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only) 2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
e16c6eb30c preparations and interface definition for memory type support 2015-02-19 20:23:08 +00:00
Stanislav Shwartsman
5e6955c5e7 Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods 2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
63c3ed3f70 update (c) and fix instrumentation stub 2015-01-11 20:50:26 +00:00
Stanislav Shwartsman
3b237df41d Added far branch origin to bx_instr_far_branch instrumentation callback by user request 
Updated instrumentation examples
Fixed code duplication
 2015-01-11 20:45:39 +00:00
Stanislav Shwartsman
d82e51f947 added comment to RDPMC instr 2014-10-15 15:28:13 +00:00
Stanislav Shwartsman
a85a9081b7 use shorter opcode names in the debug prints (skip the BX_IA_ prefix) 2013-12-02 20:06:59 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00
Stanislav Shwartsman
09254eb474 avx512 implementation fixes and next steps 2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
fd383435f0 - Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon). 
The code already knows to disasm most of the opcodes with their operands.

- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance

- Minimize amount of opcode forms in ia_opcodes.h again.
  For example Udq means the same as Wdq but with no memory form.
 2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
69f947cef2 fixes and small optimizations for avx and xop decoding 2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
2dbe81db51 first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel 2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
a277d60d89 implemented vmentering to non-active cpu state 2013-04-09 15:43:15 +00:00
Stanislav Shwartsman
d38fce8218 preparation for future extension in translate_linear - I would like to return data to caller through tlbEntry 2013-01-27 19:27:30 +00:00
Stanislav Shwartsman
4bed791ccb Added year 2013 to Copyright in all files already modified in new year 2013-01-19 20:45:03 +00:00
Stanislav Shwartsman
d93607cfe6 implemented pause threshold count in SVN + bugfix in SMAP 2013-01-08 21:03:22 +00:00
Stanislav Shwartsman
e7a2c9892c re-implement VTPF write using event handling interface as trap event (in preparation to more apic virtualization features) 2012-10-07 09:16:13 +00:00
Stanislav Shwartsman
f69bc016d2 vmx: nmi blocking after NMI event injection. better dbg print for VMEXIT 2012-10-04 16:15:58 +00:00
Stanislav Shwartsman
2ca0c6c677 Move INTR, Local APIC INTR and SVN VINTR into new event interface (hardest part) 
Minor speedup (of 1-2%) was observed due to new implementation
Remove obsolete dbg_take_irq function and dbg_force_interrupt function from CPU code, the functions were not working properly anyway
 2012-10-03 20:24:29 +00:00