mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
12,675 Commits 11 Branches 185 Tags 48 MiB
3e333a0d79
Commit Graph

73 Commits

Author SHA1 Message Date
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
c6050a99d1 implemented AVX encoded VNNI instructions published in recent SDM - not tested yet 2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
a378441254 update CPUID bits and CR bits according to recently published SDM documents by Intel 2020-10-03 07:59:47 +00:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
50bde4a38c flush TLBs on CR4.CET change 2020-01-10 20:04:22 +00:00
Stanislav Shwartsman
9458e25486 reverting commit 13737 and doing correct fix 2019-12-28 13:11:13 +00:00
Stanislav Shwartsman
5d7c6d46b0 fixed compilation after prev commit 2019-12-28 13:02:02 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
eca847c8b3 fixed compilation error 2019-12-16 19:47:41 +00:00
Stanislav Shwartsman
895c4b75df rewritten xsave/xrestore implementation in generic way to simplify adding new xsave/xrestore extensions 2019-12-16 16:14:51 +00:00
Stanislav Shwartsman
00237b5c9d add missing XSAVE_PKRU_STATE_LEN define 2019-11-12 22:02:02 +00:00
Stanislav Shwartsman
4aba3b54e7 do not use uint 2019-11-12 22:00:29 +00:00
Stanislav Shwartsman
72b9d26717 coding style changes, tab2space, macro2function or macro2const 2019-10-17 19:23:27 +00:00
Stanislav Shwartsman
6edf22e754 finally figured out what TCE means in AMD CPUID - and it has EFER.TCE bit related to it 2017-03-15 22:48:27 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
3fef7f32f6 added new bits definitions recently published 2015-06-29 19:53:56 +00:00
Stanislav Shwartsman
a197977682 fixed typo 2015-05-05 19:37:01 +00:00
Stanislav Shwartsman
16ab385e1d added cpuid/creg bits definition announced in recent 054 update of Intel SDM 2015-05-05 19:28:25 +00:00
Stanislav Shwartsman
9d8d895b52 cpuid fixes 2014-03-15 20:19:30 +00:00
Stanislav Shwartsman
2b83146ae2 more avx-512 instructions implemented 2013-12-01 19:39:18 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
fd71b03353 add some definitions introduced in recent Intel SDM extensions document (rev015) 2013-07-23 20:51:52 +00:00
Stanislav Shwartsman
c96f5e27a9 flush tlb also when cr4.smap changes 2013-01-14 17:02:51 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
ec06475dbf improve x86 hw breakpoint handling 2012-07-11 15:07:54 +00:00
Stanislav Shwartsman
6ae86a059b firt cleanup in SVM code. added intercept check for MSR and IO 2011-12-26 19:57:39 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
88a58b3781 fixed compilation with x86-64=0 2011-09-16 20:12:36 +00:00
Stanislav Shwartsman
dfd769a102 - Fixed compilation issue with cpu-level=5 
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
 2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b syscall/sysret are not supported outside long64 mode in Intel CPUs 2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
6606c62439 cr4 available since Pentium only 2011-08-16 16:49:04 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
2ee0029749 extract ffxsr support to separate CPU feature 2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
ee3f9e36cb Implemented Supervisor Mode Execution Protection (SMEP) 2011-05-29 16:28:26 +00:00
Stanislav Shwartsman
6ace540891 update for rev39 of Intel SDM 2011-05-28 20:20:25 +00:00
Volker Ruppert
c78026a9a2 - deleted executable properties from source files 2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
31dd6a70db small cleanups 2011-03-20 21:16:45 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
6deb746464 do not handle reserved bits yet 2011-03-15 20:22:17 +00:00
Stanislav Shwartsman
63fe52f601 accessors for DR6 and DR7 fields 2011-03-15 20:20:15 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
7f7c249934 disasm and some cpuid code according to recently published AVX_319433-007.pdf document 2010-07-22 15:12:08 +00:00
Stanislav Shwartsman
74b87d2b68 fixes for CPUID and alloweds bits in CRs 2010-05-12 21:33:04 +00:00
Stanislav Shwartsman
f95ddc4029 Debug Extensions was introduced in Pentium 2010-05-12 18:48:51 +00:00
Stanislav Shwartsman
ca95477b7f Implement x86-64 PCID extension 2010-04-29 19:34:32 +00:00
Stanislav Shwartsman
6d01eb5c1f announce (not implement yet) PCID 2010-03-31 14:00:46 +00:00
Stanislav Shwartsman
e7933d9dc2 enable EFER_MSR VMX controls 2010-03-27 09:27:40 +00:00
Stanislav Shwartsman
a220edc5bb compile fixes 2010-03-26 11:09:12 +00:00