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33 Commits

Author SHA1 Message Date
Stanislav Shwartsman
1089e470e9 remove bochs-memory.h from bochs.h and include it only where required 2021-01-30 20:13:34 +00:00
Stanislav Shwartsman
0b83259417 regen include dep lists for cpu and memory - need to regen for all others 2021-01-30 18:57:45 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
d6e08702e4 add Icelake-U model to CPUDB database. TODO: verify its VMX features 2019-09-24 20:26:14 +00:00
Stanislav Shwartsman
a9aa1040c1 add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions 2018-10-26 09:23:58 +00:00
Stanislav Shwartsman
5439647254 small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in 2017-10-19 21:27:25 +00:00
Stanislav Shwartsman
b2fdbd1274 added Skylake-X model to CPUDB -> with EVEX and AVX512 support 2017-08-09 20:36:17 +00:00
Volker Ruppert
dd2d03ec0a The 'del' command doesn't like forward slashes, so the MSVC nmake 'clean' 
target skipped files in subfolders. Updated cpu makefile dependencies.
 2017-03-26 15:55:57 +00:00
Volker Ruppert
8796abeea6 Some fixes in the build system. 
- Makefile: cleanup of the 'clean' target (adds missing 'bxhub').
- configure script: create cpudb subdirectories if necessary for building
  outside of the source tree.
- cpudb Makefile: clean object files from new location.
 2017-03-15 16:51:32 +00:00
Stanislav Shwartsman
07166f14b7 reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct) 2017-03-13 19:44:14 +00:00
Volker Ruppert
cd68194269 Added Android host platform support to Bochs based on SF patch #534. 
- added Android case to the configure script.
- renamed file memory.h to memory-bochs.h to fix conflict with NDK.
- fixed Android issues in some files.
 2016-08-12 17:06:14 +00:00
Stanislav Shwartsman
7a34f00f99 extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all 2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
793ceb0d8c fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header 2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
be4b73c6d2 extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class 2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
a74e855185 added Broadwell ULT CPUID definition to CPUDB 2015-02-12 21:28:24 +00:00
Stanislav Shwartsman
b60d7d3154 Cleanup of CPUDB modules, moved common functionality into bx_cpuid_t base class 
Added Pentium (P54C) AKA Pentium with no MMX to CPUDB
 2015-02-11 21:31:17 +00:00
Stanislav Shwartsman
5e6955c5e7 Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods 2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
c87605722b CPUDB: added AMD Trinity to the database 2014-03-15 18:30:13 +00:00
Stanislav Shwartsman
b335f472bd Added Haswell configuration to CPUDB 2013-06-20 19:33:30 +00:00
Stanislav Shwartsman
93d6c2e1fc added AMD Bulldozer architecture CPU (Zambezi) to CPUDB 2013-01-07 19:33:04 +00:00
Volker Ruppert
c2560a8d44 - fpu directory is now a subdirectory in 'cpu' 2012-09-12 21:08:40 +00:00
Volker Ruppert
61292eb45b - missing SHELL fixes 2012-07-14 07:13:56 +00:00
Stanislav Shwartsman
708fc666c8 Added Corei7 ivyBridge configuration to CPUDB 2012-05-07 12:31:22 +00:00
Stanislav Shwartsman
c70a42c5d7 merged patch ftom SF bug 3459998 Bochs cannot be compiled outside the source tree 2012-02-19 12:16:14 +00:00
Stanislav Shwartsman
bb7a648d91 Major commit ! 
------------

Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.

! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.

Some CPUID modules rework done to enable Toliman configuration.

Ckean up 'executable' attribute from all CPU source files.
 2012-02-13 23:29:01 +00:00
Stanislav Shwartsman
9261b2fa14 removed param_names.h include where not needed anymore 2012-01-07 17:54:19 +00:00
Stanislav Shwartsman
c857488ed9 Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-02 20:59:02 +00:00
Stanislav Shwartsman
abda3a967c added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
8ada4ce5e4 added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
Stanislav Shwartsman
c28c7f6a06 Supply real VMX capabilities together with the CPU MODEL .bochsrc option. 
So now the same single option will choose not only the CPUID flags but also VMX capabilities matching real HW machine.

Removed cpuid of core2_extreme_x9770 from the cpudb. I don't remember its VMX capabilities anyway.
There is another Penryn model in the cpudb - core2_penryn_t9600.
 2011-09-26 12:31:40 +00:00
Stanislav Shwartsman
dfd769a102 - Fixed compilation issue with cpu-level=5 
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
 2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
542af0dcc1 forgot to add a file 2011-08-18 19:02:16 +00:00