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77 Commits

Author SHA1 Message Date
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
6398ebb1d4 First step of access bits cleanup and optimization - no perf gain yet 2008-08-03 19:53:09 +00:00
Stanislav Shwartsman
4e091f2a3a Improved debug prints 2008-05-21 21:38:59 +00:00
Stanislav Shwartsman
b9f2b61fa6 Fixed CPU bug which stopped the Menuet64 OS from booting ! 2008-05-17 19:30:55 +00:00
Stanislav Shwartsman
c3f96973ba Added debug prints 2008-05-12 19:19:03 +00:00
Stanislav Shwartsman
a91ef4e31b Ignore CS.L bit when EFER.LMA is not set 
Add potentially missed CPU mode change in SYSCALL/RET/ENTER/EXIT
 2008-04-20 18:10:32 +00:00
Stanislav Shwartsman
e91409704f Convert EFER to val32 register, similar to other control registers 2008-03-31 20:56:27 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
36b1dedef5 When speculative tracing is OFF this code in ctrl_xfer_pro.cc is not needed 2008-03-22 10:42:09 +00:00
Stanislav Shwartsman
965568ea88 cleanups 2008-02-07 18:28:50 +00:00
Stanislav Shwartsman
fb0ce45d28 Unpack more fields in bxInstruction_c -> this increase bxInstruction size by 4 bytes but I have no way but do it if want to support SSE5 dest override later 2008-02-04 21:28:53 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
eee1a9030d a bit simplify and optimize shift instructions 
print failed segment info in check_cs - more debug info
 2007-12-30 20:16:35 +00:00
Stanislav Shwartsman
d9a59c7a1f Added ability to merge traces cross JCC branch instructions 
Makes traces longer -> emulation faster in average
 2007-12-14 20:41:09 +00:00
Stanislav Shwartsman
da19b9447a All Jq instructions in 64-bit mode have fixed 64-bit osize 2007-12-10 23:04:18 +00:00
Stanislav Shwartsman
48650a70b4 Optimized alignment check 2007-11-20 21:22:03 +00:00
Stanislav Shwartsman
5ec15df46d Split more opcodes EbIb opcodes 2007-11-17 18:08:46 +00:00
Stanislav Shwartsman
4ec7f5df39 Optimize access to IP (16 bit) - made IP register similar to GPR 2007-10-18 22:44:39 +00:00
Stanislav Shwartsman
8065ada31f Some EIP setting cleanups. 
OK, currently I see big mess with setting of CS/EIP and SS/ESP everywhere, I have to unify it and make it easier !
 2007-10-18 21:27:56 +00:00
Stanislav Shwartsman
e812f81e7b Fixes in zero upper ECX 2007-09-25 16:11:32 +00:00
Stanislav Shwartsman
70f513b07b Make efer control MSR separate register 2007-09-10 20:47:08 +00:00
Stanislav Shwartsman
b8787fd5a7 Some code cleanups and warning fixes 2007-03-14 21:15:15 +00:00
Stanislav Shwartsman
49d7b4614f Fixed another bug generator - duplication between descriptor type field and four descriptor cache bits 2006-06-12 16:58:27 +00:00
Stanislav Shwartsman
fe644dfcbf - Code cleanup, remove x86-64 code from functions which cannot be called from x86-64 
- Fix PANIC multiple SSE prefix decoding (fetchdecode and disasm)
- More Bit32u -> bx_phy_address convert
- Lazy flags optimization
 2006-05-12 17:04:19 +00:00
Stanislav Shwartsman
da3d26d7f4 Preliminary implemntation of SMM save statei 
Fixed fetchModeMask for load32bitOsStack
 2006-03-27 18:02:07 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU 
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
 2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
55ceecf79b Small optimization in icache page-write-stamp 2006-02-28 17:47:33 +00:00
Stanislav Shwartsman
d8ab4e3424 Fully implemented jump_far and ret_far in 64-bit mode. 
Note that I am not sure about 100% correctness, I am just coding Intel specs ...
Code review and massive testing still required.
 2005-08-02 18:44:20 +00:00
Stanislav Shwartsman
6a07173b3d Split ctrl_xfer_pro.cc to 4 different files according to the operations 2005-08-01 22:06:19 +00:00
Stanislav Shwartsman
f096a80716 Fix code duplication for check_cs descriptor 
The function will execute
 - segment is executable code segment
 - conforming/non-conforming segment priviledge checks
 - segment is present
 2005-08-01 21:40:17 +00:00
Stanislav Shwartsman
954aae3f99 Speedup push/pop operations, they actually not needed to do can_push/can_pop checkes, the same checkes already done in read/write_virtial methods 
Split push_seg_reg methods according to op size
 2005-07-31 17:57:27 +00:00
Stanislav Shwartsman
5da36b7d3d Fixed code duplication, added canonical address checking for RETF in long mode 2005-07-29 06:29:57 +00:00
Stanislav Shwartsman
dea55d5e63 Fix compilation error 2005-07-22 05:00:40 +00:00
Stanislav Shwartsman
51e03f071d Fixed XLAT instruction for x86-64 
Small optimization for lazy flags for ADD/ADC/SUB/SBB instructions
Enable RETF64 for same privelege level return
 2005-07-21 01:59:05 +00:00
Stanislav Shwartsman
aceb8c683b Initial implementation of RETF64 2005-07-20 01:26:47 +00:00
Stanislav Shwartsman
169fa0c574 Clearify the code. x86-64 code always running in pmode so it is not needed to check if we are in protected mode everytime 2005-07-10 20:32:32 +00:00
Stanislav Shwartsman
4e0ca04d31 Fixed compilation problem 2005-05-20 17:04:42 +00:00
Stanislav Shwartsman
92cc308ad2 implement the correct condition for the segment limit check 2005-05-19 19:46:20 +00:00
Stanislav Shwartsman
61946bd3a4 Fixed compilation error 2005-05-19 18:15:19 +00:00
Stanislav Shwartsman
6df9640844 implement jump_far64 for code segments 
the panic message moved to TASK-GATE64 far jmp which is still not implemented
 2005-05-19 18:13:08 +00:00
Stanislav Shwartsman
caa0648188 Move duplicated code to separate function 
And fix a bug I added by previous merge
 2005-04-17 21:51:59 +00:00
Stanislav Shwartsman
1e37312c14 Remove code duplication 2005-03-20 18:08:46 +00:00
Stanislav Shwartsman
5a393d2399 Fix for PANIC 
1162042 Duke Nukem 3D: >>PANIC<< iret: VM set on stack, CPL!=0
according to Intel and AMD docs the behaviour wasn't correct
 2005-03-12 18:09:32 +00:00
Stanislav Shwartsman
2a5a5c2de5 Fixed compilation error for 486 CPU 
small fixes for IRET instructionm
 2005-03-12 16:40:14 +00:00
Stanislav Shwartsman
031cd64827 More code review - changing BX_PANIC to BX_ERROR where implentation matches Intel docs. Also solved two cases when TS exception generated instead of GPF 2005-03-04 21:03:22 +00:00
Stanislav Shwartsman
b25088bf2f Merge patch [1153327] ignore segment bases in x86-64 by Avi Kivity 2005-02-28 18:56:05 +00:00
Stanislav Shwartsman
c583a6f9cf move segments and descriptors definitions and macroses for new descriptor.h 2005-02-27 17:41:45 +00:00
Stanislav Shwartsman
169769504e Changes BX_PANIC to BX_INFO in some more cases (patch by Kavin Lawton) 2005-02-16 19:59:03 +00:00
Stanislav Shwartsman
2ce5495d38 Fixed compilation errors 2004-11-03 06:35:48 +00:00
Stanislav Shwartsman
2ed7e4eed5 EIP > CS.limit should be checked in real mode too. 
Enable for now for JUMP instructions, still todo - CALL and RET
 2004-11-02 17:31:14 +00:00