- rombios.c: return maximum bus number #1 for i440BX.
- Now using different i/o and memory base address regions for PCI and AGP.
- Added some init code for the i440BX PCI/AGP bridge.
- Some code cleanups.
- Bochs BIOS: Improved calculating PCI slot number from device number to handle
the i440BX case correctly.
- Memory code: Detect and modify the PCI IRQ roouting table of the Bochs BIOS
for the i440BX chipset (TODO: this could be done by the BIOS itself after
copying to shadow RAM).
- Added symbols for the i440BX host bridge device ID.
- Probe and search for devices on PCI bus #1 (AGP).
- Set up memory and i/o regions only for header type 0.
- Set AGP aperture size to 64 MB.
- TODO: PCI IRQ routing, i440BX specific register setup.
- Created framework based on our I/O APIC code and ported HPET core from Qemu
with some required changes for the Bochs timer and IRQ handling.
- Enabled HPET-specific code in the ACPI and rombios32 sources and generated
new ACPI table with iasl.
- The HPET device plugin is now always loaded if the i440FX chipset is selected
(same as ACPI). We have to rethink this when we have implemented a more
modern chipset.
- TODO: Rewrite of the virtual timer code for nanosecond support to make the
realtime synchronization possible with HPET.
- renamed config parameter "i440fx_support" to "enabled"
- new config parameter "chipset" added (current choices "i430FX" and "i440FX")
- don't load ACPI support if the i430FX chipset is selected
- select register values for the core PCI devices depending on the chipset
- USB UHCI must be connected to a PCI slot if the i430FX chipset is used
- rombios changes to make the i430FX chipset work
- TODO #1: implement limitation to 1 cpu and 128 MB RAM for the i430FX chipset
- TODO #2: verify register behaviour of both chipsets
- scan for VGABIOS ROM after rombios32 init
- copy PCI ROM to shadow RAM at 0xc0000 and enable it
- NOTE: this feature does not work with BIOS-bochs-legacy, so we should recommend to use the
default BIOS for PCI display adapters
- TODO: load VGABIOS ROM from the vga code instead of main.cc if PCI is disabled
The SMBIOS spec says that at least the entry point should be between 0xf0000 and 0xfffff. Since the EBDA is currently limited to 1 KB disallow putting the SMBIOS tables there.
This should fix bug #1933859.
- Sebastian
like other PCI devices now)
- changed base address for the PCI memory space to 0xc0000000
- rombios32: fixed a warning
- fixed timeout flag for serial i/o functions
* added support for memory above the PCI hole (Izik Eidus)
* smp_probe: instead of timimg out, wait until all cpus are up (Avi Kivity)
* Bochs BIOS changes to support HPET in Qemu (Beth Kon)
- added documentation about CMOS registers set by Qemu
