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264b797363
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3428 Commits

Author SHA1 Message Date
Stanislav Shwartsman
264b797363 fixed compilation without VMX=2 2019-01-03 06:28:15 +00:00
Stanislav Shwartsman
098791bf95 report MONITOR/MWAITX for Ryzen configuration in CPUID 2018-12-01 12:15:57 +00:00
Stanislav Shwartsman
7a183ab520 fixed PDE4M reserved bits checking if physical address wider than 40 bit 2018-11-22 11:51:33 +00:00
Stanislav Shwartsman
eff201773f convert some defines to enums and const expressions 2018-11-17 12:45:44 +00:00
Stanislav Shwartsman
e387876145 Enable PML VMX feature in Skylake-X 2018-10-26 19:54:22 +00:00
Stanislav Shwartsman
2e192372c0 fixes for CNL CPUID 2018-10-26 19:46:56 +00:00
Stanislav Shwartsman
a9aa1040c1 add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions 2018-10-26 09:23:58 +00:00
Stanislav Shwartsman
cf41679b53 closing bug report: Missing TLB_flush on VMX_VMEXIT_EPT_VIOLATION 2018-08-30 20:18:27 +00:00
Stanislav Shwartsman
3995dc13aa fixed compilation of CLZERO pn cpu-level<6 2018-08-26 18:11:10 +00:00
Stanislav Shwartsman
965bcc2606 support 64-bit in 'info tab' debugger command and also speed it up significantly 2018-08-14 08:09:09 +00:00
Stanislav Shwartsman
eebdb4d63a avoid gcc 7.3 warning 2018-05-27 19:09:59 +00:00
Stanislav Shwartsman
a8413aa838 update comments base on latest AMD spec 2018-05-27 18:13:24 +00:00
Stanislav Shwartsman
fcd9ce1634 fix compilation without x86_64 2018-04-15 14:22:16 +00:00
Stanislav Shwartsman
d000e21001 added MOVDIRI opcode implementation 2018-04-06 05:06:36 +00:00
Stanislav Shwartsman
fd15b61d94 keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM 2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
8c9f7f54b6 update CPUID definitions with recently published EAS-33 extensions document 2018-04-04 18:15:44 +00:00
Stanislav Shwartsman
0cd49ddae4 fixed compilation with EVEX disabled 2018-03-29 08:50:38 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
2bca4cc310 improve debug print for SPP access 2018-01-27 21:25:46 +00:00
Stanislav Shwartsman
afc2ee6bfd Implemented SPP: EPT-Based Subpage Protection. Cleaned code duplication between FXSAVE/FXRSTORE and XSAVE/XRSTOR (save/restore of SSE code is the same) 2018-01-27 21:20:33 +00:00
Stanislav Shwartsman
a9ac81e092 convert defines to const and enum in paging.cc 2018-01-27 19:31:39 +00:00
Stanislav Shwartsman
769ed3ef88 fixed MOVBE instruction decoding 2018-01-23 19:53:34 +00:00
Stanislav Shwartsman
7d1a524ff0 fix indentation after tab2space 2018-01-11 08:47:02 +00:00
Stanislav Shwartsman
6d93ba14ec tab2space 2018-01-11 08:45:00 +00:00
Stanislav Shwartsman
3c08cfedf2 fixed buffer overflow when printing instruction disasm for opcode bytes which cannot be decoded 2017-12-31 21:22:04 +00:00
Stanislav Shwartsman
6566cab8aa fixed new disasm for avx2 opcodes 2017-12-30 18:45:21 +00:00
Stanislav Shwartsman
4c03fe3e2c fixed disasm of vcvtps2ph/ph2ps opcodes 2017-12-28 19:59:42 +00:00
Stanislav Shwartsman
27a7925810 fix for MOV to CR3 in long mode with PCID enabled - patch by Kent Williams 2017-12-25 19:49:45 +00:00
Stanislav Shwartsman
ed8fa8ac61 fix compilation with no AVX enabled 2017-12-24 15:38:21 +00:00
Stanislav Shwartsman
ca034f0642 fixed disasm of sse insertps instruction 2017-12-21 18:18:10 +00:00
Stanislav Shwartsman
59c542fb06 fix disasm of FISTTP opcodes 2017-12-19 20:36:55 +00:00
Stanislav Shwartsman
4337a062e2 disasm memsize for gather opcodes 2017-12-19 19:51:55 +00:00
Stanislav Shwartsman
15187110ef implement disasm of implicit memory reference for maskmovdqu/maskmovq opcodes. fix vmaskmovdqu disasm for legacy disasm as well 2017-12-19 19:45:30 +00:00
Stanislav Shwartsman
e086f7ba19 split INSERTPS opcode to reg and mem forms 2017-12-19 19:25:40 +00:00
Stanislav Shwartsman
ce3eafa535 disasm fix 2017-12-17 18:47:21 +00:00
Stanislav Shwartsman
79ec183ff6 fixup for MMX opcodes disasm 2017-12-17 17:21:02 +00:00
Stanislav Shwartsman
5dc5e01a12 disasm fixes and reorg of pinsr* opcodes 2017-12-16 18:34:20 +00:00
Stanislav Shwartsman
6a4e8ff2f1 fixed typo in prev commit 2017-12-13 21:08:10 +00:00
Stanislav Shwartsman
f362f34ed6 correctly decode PINSRQ instruction 2017-12-13 20:59:41 +00:00
Stanislav Shwartsman
50a799ea11 split handlers for PINSRD/Q opcodes. fix disasm for MULX instruction 2017-12-13 20:18:59 +00:00
Stanislav Shwartsman
07bff3be43 fixed decoding of VPINSRB/W/D/Q and VINSERTPS with EVEX prefix 2017-12-13 20:02:12 +00:00
Stanislav Shwartsman
8a311515dd correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only 
fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
 2017-12-13 19:51:25 +00:00
Stanislav Shwartsman
2f3c9d3c8c correct disasm for movsxd opcode 2017-12-13 18:44:13 +00:00
Stanislav Shwartsman
c1dc514c2a clarify disasm of movlhps/movhlps opcodes 2017-12-12 08:55:09 +00:00
Stanislav Shwartsman
fd953421f4 new disasm: add correct memaccess size for FLDCW 2017-12-11 19:58:09 +00:00
Stanislav Shwartsman
a84d9cf1c7 disasm: fix crc32 operand description 2017-12-11 19:45:50 +00:00
Stanislav Shwartsman
a028ef7c9c bugfix for decoder with EVEX enabled 2017-12-11 19:29:11 +00:00
Stanislav Shwartsman
e46f37b40e fixed disasm of memsize for sse legacy instructions 2017-12-11 18:33:33 +00:00
Stanislav Shwartsman
404a5f2c53 bugfix for previous commit 2017-12-11 16:41:48 +00:00
Stanislav Shwartsman
b03f78d652 updates for bochs decoder and decoder based disasm 2017-12-11 15:45:43 +00:00