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227fea6d77
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798 Commits

Author SHA1 Message Date
Stanislav Shwartsman
227fea6d77 do not check CS.limit in prefetch when in long64 mode 2005-08-05 18:23:36 +00:00
Stanislav Shwartsman
8616109eb8 revert back not correct change in fetchdecode 2005-08-05 12:53:09 +00:00
Stanislav Shwartsman
8be190d848 Implemented RDTSCP instruction 2005-08-05 12:47:33 +00:00
Stanislav Shwartsman
ea30a3ef06 Implemented CALL FAR in 64-bit mode 2005-08-04 19:38:51 +00:00
Stanislav Shwartsman
b8485d5f98 Fixed RSP checking 2005-08-04 19:31:59 +00:00
Stanislav Shwartsman
084b4fa2b2 Fixed IRET implementation for long mode 2005-08-03 21:19:11 +00:00
Stanislav Shwartsman
3681126235 Fixed ugly load_ss64/mode changing workaround in exception.cc 2005-08-03 21:10:42 +00:00
Stanislav Shwartsman
a096472646 Fixed NULL SS selector loading for ret_far 2005-08-03 21:01:02 +00:00
Stanislav Shwartsman
c6c721a450 Small fixes for call-far and others 2005-08-02 20:20:22 +00:00
Stanislav Shwartsman
d8ab4e3424 Fully implemented jump_far and ret_far in 64-bit mode. 
Note that I am not sure about 100% correctness, I am just coding Intel specs ...
Code review and massive testing still required.
 2005-08-02 18:44:20 +00:00
Stanislav Shwartsman
26f0662199 dos2unix 2005-08-01 22:18:40 +00:00
Stanislav Shwartsman
6a07173b3d Split ctrl_xfer_pro.cc to 4 different files according to the operations 2005-08-01 22:06:19 +00:00
Stanislav Shwartsman
f096a80716 Fix code duplication for check_cs descriptor 
The function will execute
 - segment is executable code segment
 - conforming/non-conforming segment priviledge checks
 - segment is present
 2005-08-01 21:40:17 +00:00
Stanislav Shwartsman
2c6393dd8b Fixed memory corruption in APIC 2005-08-01 18:55:58 +00:00
Stanislav Shwartsman
954aae3f99 Speedup push/pop operations, they actually not needed to do can_push/can_pop checkes, the same checkes already done in read/write_virtial methods 
Split push_seg_reg methods according to op size
 2005-07-31 17:57:27 +00:00
Stanislav Shwartsman
5da36b7d3d Fixed code duplication, added canonical address checking for RETF in long mode 2005-07-29 06:29:57 +00:00
Stanislav Shwartsman
2b5a812674 Split last bit.cc methods according to os16/32/64 2005-07-25 04:18:20 +00:00
Volker Ruppert
0ff15e9522 - fixed panic caused by operator precedence bug 2005-07-24 08:35:15 +00:00
Stanislav Shwartsman
dea55d5e63 Fix compilation error 2005-07-22 05:00:40 +00:00
Stanislav Shwartsman
51e03f071d Fixed XLAT instruction for x86-64 
Small optimization for lazy flags for ADD/ADC/SUB/SBB instructions
Enable RETF64 for same privelege level return
 2005-07-21 01:59:05 +00:00
Stanislav Shwartsman
aceb8c683b Initial implementation of RETF64 2005-07-20 01:26:47 +00:00
Stanislav Shwartsman
169fa0c574 Clearify the code. x86-64 code always running in pmode so it is not needed to check if we are in protected mode everytime 2005-07-10 20:32:32 +00:00
Stanislav Shwartsman
4638f09b24 Added BX_INSTR_HLT instrumentation callback 2005-07-07 18:40:35 +00:00
Stanislav Shwartsman
01d8a97613 Try to cleanup/rewrite RepeatSpeedups optimization 
This code doesn't add new speedups but makes it very easy
After some validation it could be no problem to enable repeat speedups optimization for REP MOVSx with any address size. And REP STOSx too.
 2005-07-04 17:44:08 +00:00
Stanislav Shwartsman
3d2e2162f3 Code indent, no functionality changes 2005-07-01 14:06:02 +00:00
Stanislav Shwartsman
a9dd851fd6 Fixed several PANIC cases: 
the PANIC message TSS.limit < 103 should never appear anymore
 2005-06-22 18:13:45 +00:00
Stanislav Shwartsman
ce8f1ade07 Some not really significant speedups 2005-06-21 17:01:21 +00:00
Stanislav Shwartsman
afe3ff691d Another fix for FPU tag word restore in FXRESTOR instruction (the tags were assigned to incorrect registers) 
Fixed FPU print state status word printing (printed partial status instead of normal status word)
 2005-06-18 20:46:08 +00:00
Stanislav Shwartsman
47442d437a Speedup ICAche decWriteStamp operation. The main idea for this speedup was given by h.johansson. 2005-06-16 20:28:27 +00:00
Stanislav Shwartsman
64f6d8c293 Separate force_flags function from read_flags (fix code duplication) 2005-06-16 17:25:04 +00:00
Stanislav Shwartsman
e04b4c5856 Allow zero apic timer count: 
terminate the counting if apic timer initial count register was set to zero during the counting.
 2005-06-16 16:56:30 +00:00
Stanislav Shwartsman
0b60100a0d Merged patch for Hkan T. Johansson 
TLB access bit optimizations
 2005-06-14 20:55:57 +00:00
Stanislav Shwartsman
2f4a3367e4 Fixed FPU TAG WORD restore in FXRESTOR instruction 2005-06-13 20:25:16 +00:00
Volker Ruppert
821ff1e87c - clarify operator precedence (needed by MSVC) 
- defined symbol BOCHSAPI_MSVCONLY for special cases in MSVC
 2005-06-09 17:42:34 +00:00
Stanislav Shwartsman
b5514f42de Merged patch for "compilation outside source directory" 
Added missed copyrights for APIC.CC
 2005-06-07 05:54:57 +00:00
Volker Ruppert
5e75dc3a10 - some more warnings in MSVC fixed 2005-06-06 20:14:50 +00:00
Stanislav Shwartsman
015ad92958 Added SMP status to TODO file 
Removed abusive BX_INFO from WBINVD instruction
The PREFETCHW (3DNow!) instruction should not #UD in x86-64 even on Intel w/o 3DNow!
 2005-05-27 01:53:38 +00:00
Stanislav Shwartsman
c026a90779 Unify coding style in CPU methods 
NO AFFECT ON EMULATION RESULTS
 2005-05-20 20:06:50 +00:00
Stanislav Shwartsman
4e0ca04d31 Fixed compilation problem 2005-05-20 17:04:42 +00:00
Stanislav Shwartsman
663f7d5ef3 CMPXCHG16B instruction implemented 2005-05-19 20:25:16 +00:00
Stanislav Shwartsman
92cc308ad2 implement the correct condition for the segment limit check 2005-05-19 19:46:20 +00:00
Stanislav Shwartsman
61946bd3a4 Fixed compilation error 2005-05-19 18:15:19 +00:00
Stanislav Shwartsman
6df9640844 implement jump_far64 for code segments 
the panic message moved to TASK-GATE64 far jmp which is still not implemented
 2005-05-19 18:13:08 +00:00
Stanislav Shwartsman
6c318bd047 SFENCE/MFENCE/LFENCE methods not defined in CPU class and they NOP in fetchdecode.cc 2005-05-18 05:05:40 +00:00
Kevin Lawton
f829c9cf93 Typo in CR8 handling in MOV_CqRq/MOV_RqCq had a typo. A switch 
target of 7 was used instead of 8.
 2005-05-17 22:22:35 +00:00
Stanislav Shwartsman
400b7094c6 Commit patch by kuma neko [yuubyou@gmail.com] 
64-bit IDIV uses unsigned overflow test
 2005-05-13 14:15:35 +00:00
Stanislav Shwartsman
d10731f162 Update my e-mail in source files 
Update committed SF patches in changes
 2005-05-12 18:07:48 +00:00
Stanislav Shwartsman
a86002a8bc Improve Bochs instrumentation 
Small changes in APIC timer, should fix the bug report
[ 957660 ] >>PANIC<< APIC: R(curr timer count): delta < initial
 2005-04-29 21:28:59 +00:00
Stanislav Shwartsman
dbbef1bc1a A lot of debug prints added to APIC.CC 
Comment raise of APIC_ERR_TX_ACCEPT_ERR in trigger interrupt when err already set for this vector
 2005-04-29 18:38:35 +00:00
Stanislav Shwartsman
19750b0324 Fixed highest_priority_int calculation function 
Fixed I/O APIC ID for 8CPU configuration to match BIOS tables
Remove I/O APIC initialization when INIT IPI received
 2005-04-27 18:09:27 +00:00