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68 Commits

Author SHA1 Message Date
Stanislav Shwartsman
29e3f6e762 remove trace cache disabled mode from the code. next step going to be - introducing new optimization features based on trace cache 2011-06-01 20:34:04 +00:00
Stanislav Shwartsman
1ba77b9f10 fixed defined but not used warnings 2011-05-29 20:42:47 +00:00
Stanislav Shwartsman
9aaeea3fda remove icache.h code that was added for studies in trace cache 2011-04-15 04:48:37 +00:00
Stanislav Shwartsman
74792e6841 update CHANGES 2011-04-15 04:46:27 +00:00
Volker Ruppert
c78026a9a2 - deleted executable properties from source files 2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
4de76b0571 introduced victim cache for a trace cache structure. 
Allows to significantly  cut trace cache miss latenct and find data in victim cahe instead of redoding it 
8 entries VC in parallel with direct map 64K entries
 2011-03-25 23:06:34 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
e20cbb9bf4 scan less icache entries when doing SMC flush 2011-01-23 17:21:34 +00:00
Stanislav Shwartsman
f1821fa3bf SMC invalidation only for traces that were really affected by SMC store 2011-01-23 15:54:54 +00:00
Stanislav Shwartsman
906805bb68 fix SMC detection when trace cache is not compiled in 2011-01-15 17:08:07 +00:00
Stanislav Shwartsman
f4cd9b8ac9 flush only required entries on SMC 2011-01-12 19:53:47 +00:00
Stanislav Shwartsman
fcdadabbc4 Rewritten SMC handling, removed pageWriteStamp, now trace fetch chck only for pAddr 2011-01-12 18:49:11 +00:00
Stanislav Shwartsman
fe0685c7f9 fine granular SMC detection (128b granularity used) 
significant reduction (>80%) of false SMC flushes
 2011-01-04 16:17:20 +00:00
Stanislav Shwartsman
dcc11e1b85 naming change 2010-09-28 14:18:58 +00:00
Stanislav Shwartsman
3dfcfd0ccd Split shift opcodes | optimize SAR opcode 2010-05-18 07:28:05 +00:00
Stanislav Shwartsman
d849cdf128 - Determine and select max physical address size automatically at 
configure time:
    - 32-bit physical address for 386/486 guests
    - 36-bit physical address for PSE-36 enabled Pentium guest
    - 40-bit physical address for PAE enabled P6 or later guests
 2010-05-12 14:55:12 +00:00
Stanislav Shwartsman
49934bc853 cache page split instructions 
next step - cache page split traces
 2010-05-08 08:30:04 +00:00
Stanislav Shwartsman
11b7f83a93 rename trace ilen to tlen 2010-02-13 09:41:51 +00:00
Stanislav Shwartsman
3dbb1da68a remove "dirty" pages tracking - it is too memory consuming and can fit with >4G phy addr space 2009-10-15 20:50:33 +00:00
Stanislav Shwartsman
7254ea36a1 copyright fixes + small optimization 2009-10-14 20:45:29 +00:00
Stanislav Shwartsman
6fbc9bd250 Fixed SMC when trace cache is OFF + small speedup again 2009-04-06 18:27:30 +00:00
Stanislav Shwartsman
c4eed92bb0 small optimization 2009-03-26 09:44:23 +00:00
Stanislav Shwartsman
839ef8b6ce optimizations in icache 2009-03-24 12:37:28 +00:00
Stanislav Shwartsman
e5be60be64 Fixed lazy flags bug I added in one of my prev merges 
ICACHE code reorganization
 2009-03-22 21:12:35 +00:00
Stanislav Shwartsman
4470c6a1c8 make ICACHE always enabled option and deprecate it in the configure script 
Trace cache still can be turned off
 2009-03-13 18:48:08 +00:00
Stanislav Shwartsman
9e723a044f - Added configure option to enable/disable A20 pin support. Disabling the 
A20 pin support slightly speeds up the emulation.

  - small code cleanup
 2009-03-10 16:28:01 +00:00
Stanislav Shwartsman
6fb60de2b2 cpu to see up to 40 bit physical addr space 2009-02-15 18:51:13 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
82815c4bef Put back simple hash function for icache and trace cache - more cache misses but still ~3% speedup 2008-10-14 17:23:53 +00:00
Stanislav Shwartsman
41a4527ffd Put back optimization in pageWriteStampTable 2008-07-26 15:07:14 +00:00
Stanislav Shwartsman
f303d61cc1 Fixed 'dirty page' support in debugger 2008-07-26 14:44:26 +00:00
Stanislav Shwartsman
6f7d39e832 Speedup port read to memory methods 2008-07-13 13:24:36 +00:00
Stanislav Shwartsman
a6fda9a971 Instrumentation code updated, some PANIC messages fixed 2008-06-23 02:56:31 +00:00
Stanislav Shwartsman
f642b57a54 Lazy falgs optimizations by Darek Mihocka 2008-05-04 15:07:08 +00:00
Stanislav Shwartsman
06e3615239 Reduce trace cache memory footprint using naive memory pool trace allocation 2008-05-04 05:37:36 +00:00
Stanislav Shwartsman
d9bf2b8453 Small emulation speed optimization 2008-04-19 22:29:44 +00:00
Stanislav Shwartsman
5826e2843a Inline pop/push functions 
Store only single byte of opcode in b1() - speedup shift instructions
Code cleanups
 2008-04-05 17:51:55 +00:00
Stanislav Shwartsman
aade564f33 Correct variable name 2008-03-29 21:03:38 +00:00
Stanislav Shwartsman
08f958f458 Fixed pageWriteStampTable to handle BIOS code as well - increased the table to all 4G instead of allocated memory size 
Avoid checking of pageWriteStamp in the heart of cpu loop with trace cache - now decWriteStamp will post stopTraceExecution event if it hits code page
 2008-03-29 21:01:25 +00:00
Stanislav Shwartsman
d292241102 Icache hash trick by Darek Mihocka 2008-03-21 20:02:48 +00:00
Stanislav Shwartsman
64bfbb32b5 Inline icache lookup code - speedup of 3% according to my measurements 2008-03-06 20:22:24 +00:00
Stanislav Shwartsman
e6d75f61ee Simplify icache entry calculation 2008-03-03 16:22:31 +00:00
Stanislav Shwartsman
2172e96654 small trace/iacache cleanups, always allow speculative tracing for trace cache 2008-03-03 14:35:36 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
37fbb82baa Cleanups. Move bxInstruction_c definition to separate file instr.h 2008-01-29 17:13:10 +00:00
Stanislav Shwartsman
8c9de8b4db speculative tracing on fetchdecode level 2008-01-18 09:36:15 +00:00
Stanislav Shwartsman
62c098f627 Introduce new icache hash function suggested by Darek Mihocka 
My studies show that in average new hash function of paddr + paddr>>4
suffers 5-10% less from aliasing in direct map cache array.
 2007-12-21 12:38:57 +00:00
Stanislav Shwartsman
adda3befd3 Trace cache optimization merged 2007-12-09 18:36:05 +00:00
Stanislav Shwartsman
40fc0a3e42 Reduce ICACHE back to 32K entries - reduce ICACHE size from 4M to 2M 
Not everybody already have C2D CPU with 4M L2 cache on die ...
 2007-12-04 17:34:20 +00:00
Stanislav Shwartsman
e0ee0eaaaf Diplicate ICACHE size - now index to ICACHE is exactly 16 bit so ICACHE hash function could be computed more efficiently 2007-11-22 17:32:00 +00:00