in BRANCH-smp-bochs revisions.
- The general task was to make multiple CPU's which communicate
through their APICs. So instead of BX_CPU and BX_MEM, we now have
BX_CPU(x) and BX_MEM(y). For an SMP simulation you have several
processors in a shared memory space, so there might be processors
BX_CPU(0..3) but only one memory space BX_MEM(0). For cosimulation,
you could have BX_CPU(0) with BX_MEM(0), then BX_CPU(1) with
BX_MEM(1). WARNING: Cosimulation is almost certainly broken by the
SMP changes.
- to simulate multiple CPUs, you have to give each CPU time to execute
in turn. This is currently implemented using debugger guards. The
cpu loop steps one CPU for a few instructions, then steps the
next CPU for a few instructions, etc.
- there is some limited support in the debugger for two CPUs, for
example printing information from each CPU when single stepping.
For compilers (such as Microsoft VC++) which don't allow "LL" after a
constant to make it 64-bit, this patch declares all such constants as
BX_CONST64(value). Then in config.in, a switch called
BX_64BIT_CONSTANTS_USE_LL controls whether the macro puts the
LL's in or not. Configure sets the macro, if you're on a platform
that can run such things.
- check for snprintf, strtoull
- check if empty structs allowed
- check for hash_map.h
- check for blank labels as in void main () { int x=2; label: }
- if debugger, turn on disasm too
