Commit Graph

374 Commits

Author SHA1 Message Date
Stanislav Shwartsman
359eb92c73 More fixes for CPU emulation 2008-04-19 20:00:28 +00:00
Stanislav Shwartsman
4ee1bf4b68 Fixed paging permissions for code fetch 2008-04-18 13:51:09 +00:00
Stanislav Shwartsman
5993ca527c - fixed 286 tss handling (descriptor wasn't parsed correctly)
- fixed timing of faulted instructions
- fixed PANIC message in interrupt through incorrect task gate
2008-04-18 10:19:33 +00:00
Stanislav Shwartsman
892fa99c6f - prefetch hint should be NOP when use in register mode
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
  even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
a851cfd8f0 Re-implemented modebp debugger function in simple and more clean way 2008-04-07 19:59:53 +00:00
Stanislav Shwartsman
44f04a93da Fixed compilation issue 2008-04-07 19:00:30 +00:00
Stanislav Shwartsman
fea49bb270 Fixed linear address wrap in legacy (not long64) mode 2008-04-07 18:39:17 +00:00
Stanislav Shwartsman
1b622661d7 Cleanup 2008-04-05 20:49:21 +00:00
Stanislav Shwartsman
90f1973bef Removed BX_USE_TLB - TLB is always used, only Guest2HostTLB is optional feature
Use Guest2HostTLB in prefetch code for IFETCHES - speedup above 3%
2008-04-05 20:41:00 +00:00
Stanislav Shwartsman
3f2487a0af Enabled tracing cross repeated instructions 2008-03-31 18:53:08 +00:00
Stanislav Shwartsman
231056fff4 small cleanups 2008-03-29 21:51:42 +00:00
Stanislav Shwartsman
08f958f458 Fixed pageWriteStampTable to handle BIOS code as well - increased the table to all 4G instead of allocated memory size
Avoid checking of pageWriteStamp in the heart of cpu loop with trace cache - now decWriteStamp will post stopTraceExecution event if it hits code page
2008-03-29 21:01:25 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
64bfbb32b5 Inline icache lookup code - speedup of 3% according to my measurements 2008-03-06 20:22:24 +00:00
Stanislav Shwartsman
946b7a369d Added const to fetchPtr in cpu functions 2008-03-03 15:16:46 +00:00
Stanislav Shwartsman
2172e96654 small trace/iacache cleanups, always allow speculative tracing for trace cache 2008-03-03 14:35:36 +00:00
Stanislav Shwartsman
5e7218b8c3 Fixed problem introduced by prev checkin
+
Fix beak to debugger when executing HLT instruction
2008-02-29 05:39:40 +00:00
Stanislav Shwartsman
a459a64f3e whispace, tab2space, indent, dos2unix and other cleanups 2008-02-15 22:05:43 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
8653095520 small optimization in cpu_loop with trace cache 2008-01-28 20:09:40 +00:00
Stanislav Shwartsman
9ec2c87aaa cleanups and optimizations 2008-01-22 16:20:30 +00:00
Stanislav Shwartsman
192f398b46 removed --enable-magic-breakpoint configure option - it is enabled by default if Bochs internal debugger compiled in. Also it always possible to switch magic break off by .bochsrc option 2008-01-21 21:36:58 +00:00
Stanislav Shwartsman
88a4776244 taking all CPU icache/trace cache related stuff into separate source file from cpu.cc 2008-01-17 21:15:23 +00:00
Stanislav Shwartsman
77b4b70b9b oops, revert incorrectly merged change 2008-01-10 20:32:23 +00:00
Stanislav Shwartsman
1f4608cd84 Fix for implemened 3dnow instuctions (most of them are not implemented) 2008-01-10 20:26:49 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
e7a45770fd More optimization for short traces 2008-01-05 10:45:05 +00:00
Stanislav Shwartsman
a9e001bd30 Optimize short traces 2008-01-05 10:21:25 +00:00
Stanislav Shwartsman
d891f0d8ec Fixed more VC2008 warnings - hopefully last ones 2007-12-30 17:53:12 +00:00
Stanislav Shwartsman
fc159e3bcf small cleanup 2007-12-25 21:42:38 +00:00
Stanislav Shwartsman
838fb2a048 Fixing V2008 warnings - they found a bug in sse_pfp.cc ! 2007-12-23 17:21:28 +00:00
Stanislav Shwartsman
c3c9c40674 Move MaxFetch calculation into fetchdecode - simplify the logic 2007-12-22 17:17:40 +00:00
Stanislav Shwartsman
0e5859302b Avoid 64-bit calculations when checking remainingInPage bytes 2007-12-22 12:43:17 +00:00
Stanislav Shwartsman
46366b5064 Speedup simulation by eliminating CPL==3 check from read/write_virtual* functions 2007-12-16 21:03:46 +00:00
Stanislav Shwartsman
d9a59c7a1f Added ability to merge traces cross JCC branch instructions
Makes traces longer -> emulation faster in average
2007-12-14 20:41:09 +00:00
Stanislav Shwartsman
db69a25c36 Trace cache instrumentation methods
Next step will be tracing cross non-taken branches
2007-12-14 11:27:44 +00:00
Stanislav Shwartsman
adda3befd3 Trace cache optimization merged 2007-12-09 18:36:05 +00:00
Stanislav Shwartsman
29267577f0 Fixed HLT problem in SMP binary which runs with single processor only 2007-12-08 09:26:13 +00:00
Stanislav Shwartsman
88899cf617 Changes for lazy flags handling -> 1st stap in transition to new lazy flags handling by Darek Mihocka (www.emulators.com) 2007-12-04 19:27:23 +00:00
Stanislav Shwartsman
91e0db63c4 no need to invalidate prefetch queue for RDMSR/WRMSR 2007-12-03 21:43:14 +00:00
Stanislav Shwartsman
8cfd17202a some simple SSE code optimizations 2007-11-27 22:12:45 +00:00
Stanislav Shwartsman
e51184c8cf Eliminate saving of RSP from heart of cpu_loop
Now save RSP only where it is really required
2007-11-24 14:22:34 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :)
Also split EqId G1 group for x86-64
2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
0fa82afe1f Bugfix and optimize BxResolve calls - bugfix in 64-bit mode 2007-11-13 17:30:54 +00:00
Stanislav Shwartsman
edfff23ca0 Split JCC methods to 16 different methods per branch condition 2007-11-12 18:20:15 +00:00
Stanislav Shwartsman
5a172541e2 Small cleanup 2007-11-01 20:43:53 +00:00
Stanislav Shwartsman
e137560b14 Complete MONITOR/MWAIT implemntation (including monitoring of memory range)
Fixed PANIC in read/write Cr/Dr - should #UD with unkown register used
2007-11-01 18:03:48 +00:00
Stanislav Shwartsman
ce0e0287fb Naturally speedup repeat execution functions, fix TLB index calculations 2007-10-30 22:15:42 +00:00
Stanislav Shwartsman
e9801ef501 Support for restore cpu (and any other device from bochs root) from debugger 2007-10-14 19:04:51 +00:00
Stanislav Shwartsman
ac272e9383 Changes breakpoints configure time enable macroses - reduce amount of compile-time parameters 2007-10-12 22:11:25 +00:00
Stanislav Shwartsman
dcb0335ae9 Debug first instruction in exception handler after exception 2007-09-26 18:07:39 +00:00
Stanislav Shwartsman
e812f81e7b Fixes in zero upper ECX 2007-09-25 16:11:32 +00:00
Stanislav Shwartsman
38d1f39c77 Converted CR0 bits to one register similar to CR4 - a bit slower but helps with other features implemntation 2007-07-09 15:16:14 +00:00
Stanislav Shwartsman
05ea111e1c Clean CPU debug methods in main cpu_loop 2007-03-06 17:47:18 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction
Set of minor fixes for correctness
2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
5c21f7821f Speed simulation between 3 to 5% by eliminating several checks from cpu loop.
The checks were related to repeat instructions - handle them differently
2007-01-05 13:40:47 +00:00
Stanislav Shwartsman
925ae93e22 Reveer back changes for debug.h removal from bochs.h 2006-09-26 19:16:10 +00:00
Stanislav Shwartsman
aab3feb2e0 Fixed Makefile to compile with ACPI stub disabled
Remove bx_debug.h from bochs.h to reduce compilation dependencies
2006-09-25 20:13:52 +00:00
Stanislav Shwartsman
3ab94305a0 1. Fixed bug report
[ bochs-Bugs-1562172 ] TLB_init() fails to initialize priv_check array if USE_TLB 0
2. Paging is always exists for i386+
   To disable paging it is better to use normal model without special code, only by setting cr0.pg=0
2006-09-20 17:02:20 +00:00
Stanislav Shwartsman
c7aa53d044 Fixed compilation error of extdb 2006-06-25 21:44:46 +00:00
Stanislav Shwartsman
f9754dadeb Fix some code duplication 2006-06-24 18:27:11 +00:00
Stanislav Shwartsman
070d782ec8 Move paddr_valid param of dbg_xlate_linear2phy method to return value.
This is much easier to use.
2006-06-17 12:09:55 +00:00
Stanislav Shwartsman
f44190ed27 Comment most likely redundant invalid_prefetch_q 2006-06-16 20:08:03 +00:00
Stanislav Shwartsman
8ed8916ea9 Break to debugger on triple fault or panic (this time do it correctly)
Indent changes
2006-06-12 19:51:31 +00:00
Stanislav Shwartsman
308521e7ce Fixes in SYSCALL/SYSRET instructions
Use parse_selector to avoid code duplication
2006-06-11 21:37:22 +00:00
Stanislav Shwartsman
1deddb9f0e Fix linking problem with debugger enabled 2006-06-06 16:46:08 +00:00
Stanislav Shwartsman
fea15294b5 Fixed compilation error in init.cc
Move initialization of memory object to misc_mem.cc
2006-06-03 12:59:14 +00:00
Stanislav Shwartsman
286b89d763 Several x86-64 MSRs were not-initilized !
Fixed small save-restore bug in dma.cc
First step to make save-restore code look better (only several files processed for example)
2006-05-28 17:07:57 +00:00
Stanislav Shwartsman
65e0fea773 functionally nothing changed 2006-05-26 17:24:36 +00:00
Stanislav Shwartsman
1acdb7f274 Simplify CPU loop and fix compilation error 2006-05-24 16:46:57 +00:00
Stanislav Shwartsman
8db1de7124 - Fixed several issues, each cause to NullTimer function never be called, the method is required for icache correct functionalit
- Speed-up icache by correct purging of Icache entries
- Several new assertions for timers, to prevent bugs in future
2006-05-16 20:55:55 +00:00
Stanislav Shwartsman
7acb46cd3d Small cleanup in cpu.cc 2006-05-16 16:47:00 +00:00
Stanislav Shwartsman
f4c7b4074e Support for x86-64 in x86 debugger (DR0-DR7) 2006-05-13 12:49:45 +00:00
Stanislav Shwartsman
fe644dfcbf - Code cleanup, remove x86-64 code from functions which cannot be called from x86-64
- Fix PANIC multiple SSE prefix decoding (fetchdecode and disasm)
- More Bit32u -> bx_phy_address convert
- Lazy flags optimization
2006-05-12 17:04:19 +00:00
Stanislav Shwartsman
767fb77ebd Fully handle segment limits inside prefetch method.
1. Should speed up the simulation (eliminate seg.limit check per every instruction exec)
2. Should help for DT (h.johansson request)
2006-05-04 19:54:25 +00:00
Stanislav Shwartsman
199c987ee3 Return back (modified) dbg_is_end_instr_bpoint method in cpu.cc 2006-04-29 16:14:47 +00:00
Stanislav Shwartsman
2889ed190c Removed icount guard for debugger. Implement STEPN debugger command using CPU_LOOP method capabilities 2006-04-29 09:27:49 +00:00
Stanislav Shwartsman
1a0b7ee1e3 I want to replace debugger ICOUNT guard by existent cpu_loop funtionality, first step to do that ... 2006-04-29 07:12:13 +00:00
Stanislav Shwartsman
510cbe02e2 Make fetchInstruction INLINE according to hjjhansson patch 2006-04-28 16:45:29 +00:00
Stanislav Shwartsman
ff02bc8ef0 Fixed:
With cvs snapshot 2006-04-09, --enable-debugger does not show the executed instructions anymore after being enabled via iodebug or "trace on".
2006-04-23 15:37:25 +00:00
Stanislav Shwartsman
d972e4a4b7 Fixed CR3 restore in RSM instruction
Added HALT state indication (actually make existant one working for single CPU)
2006-04-10 19:05:21 +00:00
Stanislav Shwartsman
45f30f0a4c some code written to enter CPU to shutdown state.
finally the shutdown handling should be done exactly as in VmWare - the GUI should ask user if the CPU should reset and go to HLT/IF=0 if user choosed to stay in shutdown mode.
CPU configure option reset-on-triple-failt should be extended to shutdown-reset=0|1
small code cleanups and fixes
2006-04-07 20:47:32 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash:
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
b8be848943 Use access_type param in getHostMemAddr, less efficient but no copy-paste at least 2006-03-26 19:39:37 +00:00
Stanislav Shwartsman
5c3fba4399 Support access to SMRAM in memory object
Cleanup in CPU code
2006-03-26 18:58:01 +00:00
Stanislav Shwartsman
d6f85c12f6 NMI support inside the CPU.
Added two functions to query NMI and SMI from Bochs debugger.
In future they could be used for generating NMI or SMI by user request using GUI button (could be implemented separatelly later and under configure-time or .bocshrc option)
2006-03-16 20:24:09 +00:00
Stanislav Shwartsman
e85a90a720 Remove cpu.h -> devices.cc dependancy, kill_bochs_request moved from CPU to bx_pc_system
Small Icache simplification and speedup
2006-03-14 18:11:22 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
93898e11b2 Missed } 2006-03-04 09:24:31 +00:00
Stanislav Shwartsman
324d75e749 Fix another broking change 2006-03-04 09:22:55 +00:00
Stanislav Shwartsman
7cc8bc0836 Clean and optimize 2006-03-02 17:39:10 +00:00
Stanislav Shwartsman
55ceecf79b Small optimization in icache page-write-stamp 2006-02-28 17:47:33 +00:00
Stanislav Shwartsman
79306b851c Separate fetch/decode instruction block to stand-alone method.
The method could be reused when building instruction trace for DT
2006-02-23 18:23:31 +00:00
Stanislav Shwartsman
203a9caf31 SMM mode could leave together with pmode or any other (according to amd docs)
so we need separate bx_bool indicator in_smm instead
2006-02-14 20:03:14 +00:00
Stanislav Shwartsman
024ce249bf Define SMM mode for future implementation.
I would like all next commits be aware of SMM mode.
It can't be implemented right now (too many questions w/o answers) but it will be done till next major release definitelly.
2006-02-14 19:00:08 +00:00
Stanislav Shwartsman
2646484dc1 Fix 'show' command in Boch debugger.
Fully supported show-interrupts, show-mode and show-call options
Enable toggling of show options (bug report from SF)
2006-02-12 20:21:36 +00:00
Stanislav Shwartsman
5a65e1065e Decoding functionality for Bochs disassembler.
Fixed 'step over' debugger command using bx_dbg_read_linear method.
Small debugger fix in cpu.cc
2006-02-05 19:48:29 +00:00
Stanislav Shwartsman
6ca296de8b Move --enable-reset-on-triple-fault option to runtime CPU::reste_on_triple-fault option in .bocshrc
Cleanup and optimize parser for debugger
2006-02-01 18:12:08 +00:00
Stanislav Shwartsman
37eb82c69c Totally remove the cosimulation code from Bochs.
The Bochs anyway even doesn't compile if cosimulation configured enabled.
But in the same time the cosimulation code only disturbs to the future development of Bochs debugger, for example adding x86-64 functionality ...
For those of you who still may want to see the cosimulation code inside I put it in patch and upload it Bochs CVS patches folder. Read comments for the patch ! ----------------------------------------------------------------------
2006-01-25 22:20:00 +00:00
Stanislav Shwartsman
f9cad8d272 Remove debug printf 2006-01-24 19:07:45 +00:00
Stanislav Shwartsman
18afa9fd2d This is cumulative patch for bochs debugger, it is only very first step towards working debugger supporting all new simulator functionalitieS.
- move crc.cc from debugger to bochs folder and make it projct-wide and not local for debugger
 - added new 'info sse' command for debugger
 - extend 'modebp' command to break on any mode change
 - remove unimplemened 'info program' function, it is always printed fixed text
 - move debugger help to parser, cleanup and simplify it
2006-01-24 19:03:55 +00:00
Stanislav Shwartsman
08c15c67c0 Don't know how much it helps ...
First step to make bx debugger supporting x86-64. guard_found object fields conerted to bx_address for x86-64 support.
2006-01-19 18:32:39 +00:00
Stanislav Shwartsman
2c8f6f7720 Merged patch: determine number of processors to emulate through .bochsrc 2006-01-18 18:35:38 +00:00
Stanislav Shwartsman
c92aba3776 Using back tracking in CVS I found the reason why CVS sources not compiled with configure --enable-debugger configuration (reported by Brendan).
Again it is andom change which cause to debugger not to compile ;(
This is definitelly GCC bug !
2006-01-17 07:58:11 +00:00
Stanislav Shwartsman
b07e698b3e Initialize CPU and APIC after the bx_pc_system object 2006-01-05 21:39:11 +00:00
Stanislav Shwartsman
6ff8fccfc4 Fixed cross-segment boundary check, when instruction ends on the segment boundary it should generate GP(0) 2005-12-28 19:18:50 +00:00
Stanislav Shwartsman
70cc5a7fb0 Fix incorrect commit 2005-12-12 19:54:48 +00:00
Stanislav Shwartsman
f863d1e902 Generate #GP exception instead of #TS when TSS selector points to bad TSS 2005-12-12 19:44:06 +00:00
Stanislav Shwartsman
faff702f44 GP(0) on cross segment boundaryu instruction 2005-12-09 21:21:29 +00:00
Stanislav Shwartsman
8c91790680 Redefine registers accessors in cpu.h
Change BxSupportPAE and BxSupportGlobalPages macros to Bochs style names
Set bx_cpu_id in BX_CPU_C constructor (safe way)
Backup cpu-level check for paging features at compile time (already checked in configure)
Some warnings and indent fixes
speed up get_segment_base method for x86-64 case
2005-11-26 21:36:51 +00:00
Stanislav Shwartsman
3250edb8c5 Update instrumentation 2005-11-14 18:25:41 +00:00
Stanislav Shwartsman
732abe4b30 Move parity table from cpu.cc to lazy_flags.cc 2005-10-20 17:33:36 +00:00
Stanislav Shwartsman
64ba97210b INVD/WBINVD should flush caches and TLB 2005-10-18 18:07:52 +00:00
Stanislav Shwartsman
086ee4c9aa Fix code duplication in tas 2005-08-28 17:37:37 +00:00
Alexander Krisak
7be0d52cce Added missing reinitialization of field time_tick in guard_found 2005-08-15 15:43:04 +00:00
Alexander Krisak
672ac67ff9 Fixed bug in bochs debugger caused breakpoints doesn't fires sometimes. 2005-08-15 05:32:36 +00:00
Stanislav Shwartsman
126069829d Fixed compilation error when icache is disabled 2005-08-13 14:10:22 +00:00
Stanislav Shwartsman
b192b2af9b Optimize pageWriteStamp checking 2005-08-10 18:18:57 +00:00
Stanislav Shwartsman
227fea6d77 do not check CS.limit in prefetch when in long64 mode 2005-08-05 18:23:36 +00:00
Stanislav Shwartsman
47442d437a Speedup ICAche decWriteStamp operation. The main idea for this speedup was given by h.johansson. 2005-06-16 20:28:27 +00:00
Stanislav Shwartsman
9b30cad4c4 Just software changes:
1. Separate interrupt function to 3 different functions (real_mode, long_mode, pmode)
2. Added PANIC messages for not implemented FAR CALL, FAR JUMP and FAR RET in long mode
2005-04-12 18:08:10 +00:00
Stanislav Shwartsman
1755589376 Separate pageWriteStamp from ICACHE. The pageWriteStamp has totally independant structure and could be used in future with icache structure. Also it could be significantly speeded up using BX_SMF analog constructions. 2005-04-10 19:42:48 +00:00
Stanislav Shwartsman
f77ddd9701 Remove cpu_onlline_map varaible, it wasn't initialized properly and might cause APIC problems 2005-03-19 18:43:00 +00:00
Stanislav Shwartsman
e6e9dd3825 Extend Bochs instrumentation
Compatability fixes
2005-03-17 20:50:57 +00:00
Stanislav Shwartsman
714b9c9d22 Added ICACHE statistics 2005-03-10 21:22:15 +00:00
Stanislav Shwartsman
b25088bf2f Merge patch [1153327] ignore segment bases in x86-64 by Avi Kivity 2005-02-28 18:56:05 +00:00
Stanislav Shwartsman
799403620e Small speedup in boundaryFetch method 2005-02-12 14:00:13 +00:00
Stanislav Shwartsman
e6efa3a451 - exceeding the instruction length limit of 15 bytes (this only can
occur when redundant prefixes are placed before an instruction)
    generate #GP(0) (Stanislav)
2005-02-05 20:56:44 +00:00
Stanislav Shwartsman
3cd646004f Fixed bug "1101168 APIC base address change" 2005-01-13 19:03:40 +00:00
Stanislav Shwartsman
bf0fc24cd5 Fixed icache uncompetability with physical addresses > mem.len 2004-11-19 09:39:30 +00:00
Stanislav Shwartsman
645e04860e For now : disable fetching from physical address 0xFFFFFFF0 after #RESET
because ICACHE do not support physical address > mem.len.
This is the first part of the fix, the rest coming soon
2004-11-18 23:16:36 +00:00
Stanislav Shwartsman
c482fbed43 Add additional debug info 2004-11-15 19:38:42 +00:00
Volker Ruppert
3cad938b05 - gdbstub support turned into a runtime option (SF patch #1021740 by Charles Duffy)
- gdb_* options moved to the new gdbstub option
2004-11-06 10:50:03 +00:00
Stanislav Shwartsman
41daacdf80 fixed BX_CPU_THIS pointers 2004-11-05 10:13:15 +00:00
Stanislav Shwartsman
a9022ac5cb Fixed compilation prroblem reported in bug
[ bochs-Bugs-913418 ] compiler errors with --enable-external-debugger option
Remove code duplication
2004-10-29 21:15:48 +00:00
Stanislav Shwartsman
75e0c5b421 Little speed optimizations in cpu_loop function
change apic classes to more c++ friendly
2004-10-16 19:34:17 +00:00
Stanislav Shwartsman
bbd55fe16f Merge and commit patch.apic-zwane from CVS patches directory.
the patch release notes by Zwane:

o Define symbols for constants like
o APIC arbitration
o Processor priority
o Various interrupt delivery fixes
o Focus processor checking
o ExtINT delivery

I need to release this now so that i don't fall too far behind CVS, when
it was part of the bochs-smp patch it could boot 2.4.18 4way. Apologies
for the whitespace changes.


Also remove patch.apic-ppr-zwane patch because it already included in
patch.apic-zwane.

I hope it will help to boot x86-64 or cmp systems required missed APIC
features !
2004-09-15 21:48:57 +00:00
Stanislav Shwartsman
6cdb42d909 Little bit optimize memory access functions. Now values are calculated only if they actually needed. 2004-09-13 20:48:11 +00:00
Stanislav Shwartsman
789ed4da04 Removed debug print 2004-07-29 20:30:14 +00:00
Stanislav Shwartsman
f9bd2b74be 1. Fixed bug in FSUB instruction
2. Fixed bug

[ 989478 ] I-Cache and undefined Instruktions

The L4 microkernel uses an undefined instruction to
trap for a special requests into the kernel (LOCK NOP).
The handler fixes this up and gives the user a special
code page with syscall stubs. If you're not using the
I-Cache optimization everthing works find on bochs. But
if you enable the I-Cache (--enable-icache), then the
undefined opcode exception is thrown only once for ever
virtual address it occurs. See the demodisk of the
L4KA::pistachio
(http://www.l4ka.org/projects/pistachio/download.php).
In this case the pingpong benchmark of this demo is of
interest. Everything runs fine until the program tries
to spawn a new task for its measurements. This new task
shares the code of the creating program. But the new
task stops executing at the undefined instruction
explained above and no exception is thrown.
2004-07-29 20:15:19 +00:00
Stanislav Shwartsman
5873b26a82 Speed up compilation process.
bochs.h already not include iodev.h which reduces compilation dependences for almost all cpu and fpu files, now cpu files will not be recompiled if iodev includes was changed
2004-06-19 15:20:15 +00:00
Michael Brown
d1922bc835 Changed #ifdef MAGIC_BREAKPOINT to #if BX_MAGIC_BREAKPOINT and added a
configure script option --enable-magic-breakpoints (enabled by default).

Documented the instruction required to trigger the magic breakpoint
(xchgw %bx,%bx).
2004-01-29 17:49:03 +00:00
Daniel Gimpelevich
ae66bb33c0 Applied Russ Cox's CPU panic debug patch from Oct 2003. 2004-01-17 08:36:29 +00:00
Stanislav Shwartsman
d5210af668 Two new bx_instrumentation callbacks 2003-10-09 19:05:13 +00:00
Alexander Krisak
45df735c30 Apply Vitaly's Vorobyov debugger patch 2003-08-04 16:03:09 +00:00
Volker Ruppert
d1652093ac - applied some parts of the patch from Andrew Zabolotny <zap@cobra.ru>
* changed all %ll format descriptions to FMT_LL macro so that
    Microsoft Visual C works correctly (it uses %I64)
  * missing type conversions added
  * cdrom.cc: variable types for win32 fixed
  * removed some unused variables in eth_win32.cc and harddrv.cc
  * added missing includes in make_cmos_image.c and niclist.c
2003-06-07 19:16:55 +00:00
Stanislav Shwartsman
777e0db06b Fixed cpu.cc compilation error with ICache disabled
Added --enable-3dnow configuration option
2003-05-21 15:48:55 +00:00
Kevin Lawton
a17d06abcb Optimized the main cpu loop iCache checks to remove a redundant
check.

Commented out a number of instances of invalidate_prefetch_q(),
for branches which do not change CS since the EIP window mechanism
takes care of validating that EIP lands in the current page or not
in the main cpu loop anyways.

Fixed a couple cases (v8086 mode and real mode) of loading CS where
the EIP page window was not invalidated in segment_ctrl_pro.cc.
That may fix some aliasing problems reported before (OS2).
2003-05-10 22:25:55 +00:00
Christophe Bothamy
1a518b81fe - add __attribute__((regparm(X))) performance trick with gcc on x86
on some cpu instructions (patch from Conn Clark)
- performance improvement is 1% on win95 boot
2003-03-17 00:41:01 +00:00
Peter Tattam
94880d1412 Fix guest2host and related optimizations to work on 64 bit host.
1) fixed the type of "hostPageAddr" and associated typecasts.
2) fixed the type of "pages" and associated typecasts (overloaded variable)
3) patch to cpu.cc to calculate "eipPageBias" correctly in 64 bit mode
2003-02-28 02:37:18 +00:00
Stanislav Shwartsman
cdfc3cbce4 instrumentation enchancements:
* renamed CPU_ID to BX_CPU_ID.
  with this new name there is no possibility for name contentions and BX_CPU_ID
  definition could be moved out to NEED_CPU_REG_SHORTCUTS block

* returned back `unsigned BX_CPU::which_cpu(void)` function

* added BX_CPU_ID parameter for
	BX_INSTR_PHY_READ(a20addr, len);
	BX_INSTR_PHY_WRITE(a20addr, len);
    now it will be
	BX_INSTR_PHY_READ(cpu_id, a20addr, len);
	BX_INSTR_PHY_WRITE(cpu_id, a20addr, len);
2003-02-13 15:04:11 +00:00
Stanislav Shwartsman
9c5c40e8ce Fixed BX_INSTR_OPCODE call when instruction was found in the ICache 2002-12-26 20:22:35 +00:00
Stanislav Shwartsman
f2f976d736 Add BX_INSTR_FETCH_DECODE_COMPLETED call even if an instruction hitten in ICache 2002-12-20 13:36:50 +00:00
Christophe Bothamy
3104ba6bea - fix [ 625878 ] reset doesn't reset something(?)
In bx_cpu_c::reset method I set bx_cpu->async_event to 2
  so execution in the cpu_loop gets stopped early.

  Previously, async_event was set to 0, and with repeatable
  instructions, after reset, eip was incremented by the instruction
  length, so execution would resume at 0xffffX (X being >0, the current
  instruction length).

  In halt state I check now for reset with async_event is 2, so
  reset works also when the cpu is halted. (update to Peter change)

  I hope I fixed this the right way, please report any strange behaviour.
2002-11-21 08:08:29 +00:00
Peter Tattam
1bb5040031 Miscellaneous patches for Tattam's External Debugger.
- Now compiles for plain ia-32
- Fixed some printf formatting for ia32 only.
- Update to latest Win32 DLL
- Added an ICEBP (Undoc 0xF8, INT 01) facility.
- updated to use latest VGA refresh routine
2002-11-04 05:27:26 +00:00
Bryce Denney
48acd53db4 - all #warnings are now inside #ifdef __GNUC__ ... #endif
Modified Files:
    ltdl.c main.cc plugin.cc cpu/cpu.cc cpu/debugstuff.cc
    cpu/exception.cc cpu/fetchdecode64.cc cpu/init.cc
    cpu/paging.cc gui/siminterface.cc gui/wxmain.cc
    iodev/harddrv.cc
2002-10-25 12:36:44 +00:00
Bryce Denney
cec9135e9f - Apply patch.replace-Boolean rev 1.3. Every "Boolean" is now changed to a
"bx_bool" which is always defined as Bit32u on all platforms.  In Carbon
  specific code, Boolean is still used because the Carbon header files
  define it to unsigned char.
- this fixes bug [ 623152 ] MacOSX: Triple Exception Booting win95.
  The bug was that some code in Bochs depends on Boolean to be a
  32 bit value.  (This should be fixed, but I don't know all the places
  where it needs to be fixed yet.)  Because Carbon defined Boolean as
  an unsigned char, Bochs just followed along and used the unsigned char
  definition to avoid compile problems.  This exposed the dependency
  on 32 bit Boolean on MacOS X only and led to major simulation problems,
  that could only be reproduced and debugged on that platform.
- On the mailing list we debated whether to make all Booleans into "bool" or
  our own type.  I chose bx_bool for several reasons.
  1. Unlike C++'s bool, we can guarantee that bx_bool is the same size on all
     platforms, which makes it much less likely to have more platform-specific
     simulation differences in the future.  (I spent hours on a borrowed
     MacOSX machine chasing bug 618388 before discovering that different sized
     Booleans were the problem, and I don't want to repeat that.)
  2. We still have at least one dependency on 32 bit Booleans which must be
     fixed some time, but I don't want to risk introducing new bugs into the
     simulation just before the 2.0 release.

Modified Files:
    bochs.h config.h.in gdbstub.cc logio.cc main.cc pc_system.cc
    pc_system.h plugin.cc plugin.h bios/rombios.c cpu/apic.cc
    cpu/arith16.cc cpu/arith32.cc cpu/arith64.cc cpu/arith8.cc
    cpu/cpu.cc cpu/cpu.h cpu/ctrl_xfer16.cc cpu/ctrl_xfer32.cc
    cpu/ctrl_xfer64.cc cpu/data_xfer16.cc cpu/data_xfer32.cc
    cpu/data_xfer64.cc cpu/debugstuff.cc cpu/exception.cc
    cpu/fetchdecode.cc cpu/flag_ctrl_pro.cc cpu/init.cc
    cpu/io_pro.cc cpu/lazy_flags.cc cpu/lazy_flags.h cpu/mult16.cc
    cpu/mult32.cc cpu/mult64.cc cpu/mult8.cc cpu/paging.cc
    cpu/proc_ctrl.cc cpu/segment_ctrl_pro.cc cpu/stack_pro.cc
    cpu/tasking.cc debug/dbg_main.cc debug/debug.h debug/sim2.cc
    disasm/dis_decode.cc disasm/disasm.h doc/docbook/Makefile
    docs-html/cosimulation.html fpu/wmFPUemu_glue.cc
    gui/amigaos.cc gui/beos.cc gui/carbon.cc gui/gui.cc gui/gui.h
    gui/keymap.cc gui/keymap.h gui/macintosh.cc gui/nogui.cc
    gui/rfb.cc gui/sdl.cc gui/siminterface.cc gui/siminterface.h
    gui/term.cc gui/win32.cc gui/wx.cc gui/wxmain.cc gui/wxmain.h
    gui/x.cc instrument/example0/instrument.cc
    instrument/example0/instrument.h
    instrument/example1/instrument.cc
    instrument/example1/instrument.h
    instrument/stubs/instrument.cc instrument/stubs/instrument.h
    iodev/cdrom.cc iodev/cdrom.h iodev/cdrom_osx.cc iodev/cmos.cc
    iodev/devices.cc iodev/dma.cc iodev/dma.h iodev/eth_arpback.cc
    iodev/eth_packetmaker.cc iodev/eth_packetmaker.h
    iodev/floppy.cc iodev/floppy.h iodev/guest2host.h
    iodev/harddrv.cc iodev/harddrv.h iodev/ioapic.cc
    iodev/ioapic.h iodev/iodebug.cc iodev/iodev.h
    iodev/keyboard.cc iodev/keyboard.h iodev/ne2k.h
    iodev/parallel.h iodev/pci.cc iodev/pci.h iodev/pic.h
    iodev/pit.cc iodev/pit.h iodev/pit_wrap.cc iodev/pit_wrap.h
    iodev/sb16.cc iodev/sb16.h iodev/serial.cc iodev/serial.h
    iodev/vga.cc iodev/vga.h memory/memory.h memory/misc_mem.cc
2002-10-25 11:44:41 +00:00
Bryce Denney
5e520261db Add plugin support to Bochs by merging all the changes from the
BRANCH_PLUGINS branch!

Authors:
  Bryce Denney
  Christophe Bothamy
  Kevin Lawton (we grabbed a lot of plugin code from plex86)
Testing help from:
  Volker Ruppert
  Don Becker (Psyon)
  Jeremy Parsons (Br'fin)

The change log is too long to paste in here.  To read the change log, do
  cvs log patches/patch.final-from-BRANCH_PLUGINS.gz

All the changes and a detailed description are contained in a patch
called patch.final-from-BRANCH_PLUGINS.gz.  To look at the complete
patch, do
  cvs upd -r1.1 patches/patch.final-from-BRANCH_PLUGINS.gz

Then you will have a local copy of the patch, which you can gunzip and
play with however you want.

Modified Files:
    .bochsrc Makefile.in aclocal.m4 bochs.h config.h.in configure
    configure.in gdbstub.cc logio.cc main.cc pc_system.cc
    pc_system.h state_file.h bios/Makefile.in bios/rombios.c
    cpu/Makefile.in cpu/access.cc cpu/apic.cc cpu/arith16.cc
    cpu/arith32.cc cpu/arith8.cc cpu/cpu.cc cpu/cpu.h
    cpu/ctrl_xfer32.cc cpu/exception.cc cpu/fetchdecode.cc
    cpu/fetchdecode64.cc cpu/flag_ctrl.cc cpu/flag_ctrl_pro.cc
    cpu/init.cc cpu/io.cc cpu/logical16.cc cpu/logical32.cc
    cpu/logical8.cc cpu/paging.cc cpu/proc_ctrl.cc
    cpu/protect_ctrl.cc cpu/segment_ctrl_pro.cc cpu/shift16.cc
    cpu/shift32.cc cpu/stack64.cc cpu/string.cc cpu/tasking.cc
    debug/Makefile.in debug/dbg_main.cc disasm/Makefile.in
    doc/docbook/user/user.dbk dynamic/Makefile.in fpu/Makefile.in
    gui/Makefile.in gui/amigaos.cc gui/beos.cc gui/carbon.cc
    gui/control.cc gui/control.h gui/gui.cc gui/gui.h
    gui/keymap.cc gui/keymap.h gui/macintosh.cc gui/nogui.cc
    gui/rfb.cc gui/sdl.cc gui/sdlkeys.h gui/siminterface.cc
    gui/siminterface.h gui/term.cc gui/win32.cc gui/wx.cc
    gui/wxdialog.cc gui/wxdialog.h gui/wxmain.cc gui/wxmain.h
    gui/x.cc gui/keymaps/sdl-pc-de.map gui/keymaps/sdl-pc-us.map
    gui/keymaps/x11-pc-de.map instrument/example0/instrument.h
    instrument/example1/instrument.h
    instrument/stubs/instrument.cc instrument/stubs/instrument.h
    iodev/Makefile.in iodev/biosdev.cc iodev/biosdev.h
    iodev/cdrom.cc iodev/cmos.cc iodev/cmos.h iodev/devices.cc
    iodev/dma.cc iodev/dma.h iodev/eth_fbsd.cc iodev/eth_linux.cc
    iodev/eth_null.cc iodev/eth_tap.cc iodev/floppy.cc
    iodev/floppy.h iodev/guest2host.cc iodev/guest2host.h
    iodev/harddrv.cc iodev/harddrv.h iodev/iodebug.cc
    iodev/iodebug.h iodev/iodev.h iodev/keyboard.cc
    iodev/keyboard.h iodev/ne2k.cc iodev/ne2k.h iodev/parallel.cc
    iodev/parallel.h iodev/pci.cc iodev/pci.h iodev/pci2isa.cc
    iodev/pci2isa.h iodev/pic.cc iodev/pic.h iodev/pit.cc
    iodev/pit.h iodev/pit_wrap.cc iodev/pit_wrap.h iodev/sb16.cc
    iodev/sb16.h iodev/scancodes.cc iodev/scancodes.h
    iodev/serial.cc iodev/serial.h iodev/slowdown_timer.cc
    iodev/slowdown_timer.h iodev/unmapped.cc iodev/unmapped.h
    iodev/vga.cc iodev/vga.h memory/Makefile.in memory/memory.cc
    memory/memory.h memory/misc_mem.cc misc/bximage.c
    misc/niclist.c
Added Files:
    README-plugins extplugin.h ltdl.c ltdl.h ltdlconf.h.in
    ltmain.sh plugin.cc plugin.h
2002-10-24 21:07:56 +00:00
Stanislav Shwartsman
c5f0ef8c76 Removed duplicated definition of BX_SEG_REGS 2002-10-16 22:10:07 +00:00
Kevin Lawton
b8d7f5c88e Moved the asm() statements from the arithmetic instruction emulation
into inline functions with asm() statements in cpu.h.  This cleans
  up the *.cc code (which now doesn't have any asm()s in it), and
  centralizes the asm() code so constraints can be modified in one
  place.  This also makes it easier to cover more instructions
  with asm()s for more efficient eflags handling.
2002-10-07 22:51:58 +00:00
Kevin Lawton
d7a16521c4 Replaced "return;" statements associated with bx_guard.special_unwind_stack
hack with longjmp() back to cpu.cc main decode loop, and added a
  check in there to return control when bx_guard.special_unwind_stack
  is set (compiling with debugger enabled only).

If in the debugger you try to execute further instructions
  (which you shouldn't), other fields need to be reset I would
  think, such as EXT and errorno, and have to make sure ESP/EIP
  are corrected properly.  Basically, this hack is only good
  for examining the current situation of a nasty fault.
2002-10-06 22:08:18 +00:00
Kevin Lawton
b1d2f7ae48 Added a return value to handleAsyncEvent() so that requests to
exit out of cpu_loop() and back to the caller can be honored.
  Previously, code in this function was a part of cpu_loop so
  a "return;" would already do that.  Now, a value is passed
  back to cpu_loop() to denote such a request, and then a return
  is executed from cpu_loop().

  I haven't tested this yet, but previously I must have broke
  certain debugging requests by moving the code to a separate
  function and not fixing the "return;" statements.
2002-10-05 14:51:25 +00:00
Peter Tattam
db0a37824c Fixed elusive APIC interrupt problems when bochs compiled for P6 or later.
Symptom:  Linux kernel 2.4.19 would hang in random places.  CPU still
running, but in dle loop.

Cause: if APIC interrupt occurred while a PIC interrupt was pending, the
PIC interrupt would be lost.  This is because either an APIC or PIC
interrupt would trash any pending interrupt event because INTR is only a state,
not an event queue.

Temporary fix: reworked apic.cc to have it's own copy of INTR state. cpu.cc now
checks for both cpu.INTR and local_apic.INTR.

Need to do further research to see if local_apic and pic can be integrated in such
a way as properly manage the combined effects of both devices accessing INTR state.
2002-10-05 10:25:31 +00:00
Kevin Lawton
66452e9898 Replaced tabs in cpu/*.{cc,h} files with spaces. 2002-10-04 17:04:33 +00:00
Kevin Lawton
f64eb0e16a Changed the hot countdown timer in pc_system.* files to be
32-bits rather than 64.  This is possible, because there is
  always an active null (heartbeat) timer, with periodicity
  of less than or equal to the maximum 32-bit int value.

  This generates a little less code in the hot part of cpu_loop,
  and saved about 3% execution time on a Win95 boot.

Moved the asynchronous handling code from cpu_loop() to its
  own function since it's a long path.  This neatened up the
  code a little (less gotos and all), and made it more clear
  to use a "while (1)" around the iterative code in cpu_loop().
2002-10-04 16:26:10 +00:00
Bryce Denney
75ce3842d2 - add GDB stub patch by Johan Rydberg 2002-10-03 05:14:50 +00:00
Peter Tattam
94b2dd2bc8 Cleanup of extdb.* files. included in right places now. 2002-10-01 04:13:12 +00:00
Kevin Lawton
67721c48f4 The convience functions protected_mode(), v8086_mode() and real_mode()
now simply return a cached value which is set upon mode changes.
  The biggest problem was protected_mode() which did something like:

    return CR0.PM && ! EFLAGS.VM

  This adds up when it was being executed many times in branch functions
  etc.  Now, cached values are set and sampled instead.
2002-09-29 22:38:18 +00:00
Stanislav Shwartsman
abb1530faf Fixed number of problems with instrumentation merge cause to instrumentation fail the compilation 2002-09-29 15:06:58 +00:00
Stanislav Shwartsman
8d99157993 Another additional for instrumentation 2002-09-29 14:16:30 +00:00
Stanislav Shwartsman
d495bd75a6 fter integration of SplitMod11b changes Bochs failed to compile in SMP mode.
I fixed the compilation errors in CVS, smbd please check if the fix is property;
2002-09-28 09:38:58 +00:00
Kevin Lawton
13a1e55f20 Committed patches/patch-bochs-instrumentation from Stanislav.
Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc,
and cpu.cc since the original patches, so I did some patch
integration by hand.  Check the placement of the
macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE()
in cpu.cc to make sure I go them right.  Also, I changed the
parameters to BX_INSTR_OPCODE() to update them to the new code.
I put some comments before each of these to help determine if
the placement is right.

These macros are only compiled in if you are gathering instrumentation
data from bochs, so they shouldn't effect others.
2002-09-28 00:54:05 +00:00
Kevin Lawton
3c09fdb363 I updated code that was using !!get_CF() (or other arithmetic flag) to
use getB_CF() etc.  getB_CF() and friends are only for a relatively
  small number of cases where a true boolean/binary number (0 or 1) is required
  rather than 0 or non-0 as is returned by get_CF().
2002-09-24 18:33:38 +00:00
Kevin Lawton
41929b75bd Moved the "i = &iStorage" line inside the #ifdef bracketing
for iCache support.  It wouldn't hurt anything, but it
  makes the compiler complain of longjmp/fork issues.
2002-09-22 23:42:01 +00:00
Kevin Lawton
b742ccec7e Changed eflags accessors for get_?F() to use (val32 & (1<<N)) instead
of (1 & (val32>>N)), and added a getB_?F() accessor for special
  cases which need a strict binary value (exactly 0 or 1).  Most
  code only needed a value for logical comparison.  I modified the
  special cases which do need a binary number for shifting and
  comparison between flags, to use the special getB_?F() accessor.

Cleaned up memory.cc functions a little, now that all accesses
  are within a single page.

Fixed a (not very likely encountered) bug in fetchdecode.cc (and
  fetchdecode64.cc) where a 2-byte opcode starting with a prefix
  starts at the last offset on a page.  There were no checks
  on the segment overrides for a boundary condition.  I added them.

The eflags enhancements added just a tiny bit of performance.
2002-09-22 18:22:24 +00:00
Kevin Lawton
3bfeab23c9 Split out JZ/JNZ instructions from JCC because they were called
so frequently.
Coded asm() statements for INC/DEC_ERX() instructions.
Cleaned up the iCache a litle including a bug fix.  The
  generation ID was decrementing the whole field including
  some high meta bits.  That could roll over after 1 Billion
  cycles.  I know only decrement if the field is valid, to
  save the write.
I implemented inline functions which can serve the value of
  the arithmetic flags if they are cached, and redirect to
  the lazy_flags.cc routines if not.
Most of this was just prep work for adding more asm() statements
  for native eflags processing when on x86.
2002-09-22 01:52:21 +00:00
Kevin Lawton
402d02974d Moved the EFLAGS.RF check and clearing of inhibit_mask code
in cpu.cc out of the main loop, and into the asynchronous
events handling.  I went through all the code paths, and
there doesn't seem to be any reason for that code to be
in the hot loop.

Added another accessor for getting instruction data, called
modC0().  A lot of instructions test whether the mod field
of mod-nnn-rm is 0xc0 or not, ie., it's a register operation
and not memory.  So I flag this in fetchdecode{,64}.cc.
This added on the order of 1% performance improvement for
a Win95 boot.

Macroized a few leftover calls to Write_RMV_virtual_xyz()
that didn't get modified in the x86-64 merge.  Really, they
just call the real function for now, but I want to have them
available to do direct writes with the guest2host TLB pointers.
2002-09-20 03:52:59 +00:00
Kevin Lawton
0cd7346b9c - Added an instruction cache. Size is fixed for the moment,
but if you hand edit cpu/cpu.h, and change BxICacheEntries,
  you can try different sizes.  I'll make this more flexible
  with configure.  For now, use "--enable-icache" with no parameters.

- Modified fetchdecode.cc/fetchdecode64.cc just enough so that
  instructions which encode a direct address now use a memory
  resolution function which just sticks the immediate address
  into rm_addr.  With cached instructions we need this.
2002-09-19 19:17:20 +00:00
Kevin Lawton
4e51dcae40 Converted all the remaining available separate fields in bxInstruction_c
to bitfields.  bxInstruction_c is now 24 bytes, including 4 for
the memory addr resolution function pointer, and 4 for the
execution function pointer (16 + 4 + 4).

Coded more accessors, to abstract access from most code.
2002-09-18 08:00:43 +00:00
Kevin Lawton
6723ca9bf4 Moved more separate fields in the bxInstruction_c into bitfields
with accessors.  Had to touch a number of files to update the
access using the new accessors.

Moved rm_addr to the CPU structure, to slim down bxInstruction_c
and to prevent future instruction caching from getting sprayed
with writes to individual rm_addr fields.  There only needs to
be one.  Though need to deal with instructions which have
static non-modrm addresses, but which are using rm_addr since
that will change.

bxInstruction_c is down to about 40 bytes now.  Trying to
get down to 24 bytes.
2002-09-18 05:36:48 +00:00
Kevin Lawton
07b0df2a8a Updated accessing of modrm/sib addressing information to
use accessors.  This lets me work on compressing the
size of fetch-decode structure (now called bxInstruction_c).

I've reduced it down to about 76 bytes.  We should be able
to do much better soon.  I needed the abstraction of the
accessors, so I have a lot of freedom to re-arrange things
without making massive future changes.

Lost a few percent of performance in these mods, but my
main focus was to get the abstraction.
2002-09-17 22:50:53 +00:00
Kevin Lawton
80dd7a07ec Removed references to building libextdb.a. It doesn't seem to
be used at all, and Peter didn't want it.  "extdb.o" is compiled
into libcpu.a, if configured for it.

Removed a few #warnings for x86-64 compile, based on Peter's
line-item comments regarding the warnings I inserted during
the port/merge.
2002-09-15 15:10:21 +00:00
Kevin Lawton
0305a6a2fa (cpu64) Merged {cpu,cpu64}/cpu.h 2002-09-14 03:01:05 +00:00
Bryce Denney
5fc31bcfda - this revision changes the way eflags are accessed throughout the cpu and
cpu64 directories.  Instead of using the macros introduced in cpu.h rev 1.37
  such as GetEFlagsDFLogical and SetEFlagsDF and ClearEFlagsDF, I made inline
  methods on the BX_CPU_C object that access the eflags fields.  The problem
  with the macros is that they cannot be used outside the BX_CPU_C object.  The
  macros have now been removed, and all references to eflags now use these new
  accessors.
- I debated whether to put the accessors as members of the BX_CPU_C object
  or members of the bx_flags_reg_t struct.  I chose to make them members
  of BX_CPU_C for two reasons: 1. the lazy flags are implemented as
  members of BX_CPU_C, and 2. the eflags are referenced in many many places
  and it is more compact without having to put eflags in front of each.  (The
  real problem with compactness is having to write BX_CPU_THIS_PTR in front of
  everything, but that's another story.)
- Kevin pointed out a major bug in my set accessor code.  What a difference a
  little tilde can make!  That is fixed now.
- modified: load32bitOShack.cc debug/dbg_main.cc
  and in both cpu and cpu64 directories:
    cpu.cc cpu.h ctrl_xfer_pro.cc debugstuff.cc exception.cc flag_ctrl.cc
    flag_ctrl_pro.cc init.cc io.cc io_pro.cc proc_ctrl.cc soft_int.cc
    string.cc vm8086.cc
2002-09-12 18:10:46 +00:00
Bryce Denney
0fdbbae45b - integrate Peter Tattam's x86-64 emulation code into the main branch!
This adds a whole new directory cpu64 with the new emulation code.
  Very few changes were necessary outside cpu64.  To try it, configure
  with --enable-x86-64 and make.
- also this adds Peter Tattam's external debugger interface.
- modified files: Makefile.in bochs.h config.h.in configure.in
  load32bitOShack.cc logio.cc cpu/Makefile.in cpu/cpu.cc debug/dbg_main.cc
- added files: cpu/extdb.cc cpu/extdb.h and cpu64/*
2002-09-12 07:16:37 +00:00
Bryce Denney
f4818e6fa3 - bug fix from Peter Tattam that he describes as follows:
> This is the bug fix to make the reset button work properly when the cpu
  > is in the halt state.  There is another patch in init.cc as well to clear
  > async_event.  If you don't do this, if a cpu goes into HLT, the only thing
  > which will fix it is another interrupt.  The reset button won't work.
2002-09-12 06:29:13 +00:00
Kevin Lawton
0d7a5fdf3c I rehashed the way the EFLAGS register was stored internally.
All the EFLAGS bits used to be cached in separate fields.  I left
a few of them in separate fields for now - might remove them
at some point also.  When the arithmetic fields are known
(ie they're not in lazy mode), they are all cached in a
32-bit EFLAGS image, just like the x86 EFLAGS register expects.
All other eflags are store in the 32-bit register also, with
a few also mirrored in separate fields for now.

The reason I did this, was so that on x86 hosts, asm() statements
can be #ifdef'd in to do the calculation and get the native
eflags results very cheaply.  Just to test that it works, I
coded ADD_EdId() and ADD_EwIw() with some conditionally compiled
asm()s for accelerated eflags processing and it works.

-Kevin
2002-09-08 04:08:14 +00:00
Kevin Lawton
3f2d28f86c Added guest2host TLB tricks to read-modify-write variants of
access routines in access.cc, completing the upgrade of
those routines.  You do need '--enable-guest2host-tlb', before
you get the speedups for now.  The guest2host mods seem pretty
solid, though I do need to see what effects the A20 line has
on this cache and the paging TLB in general.
2002-09-03 04:54:28 +00:00
Kevin Lawton
746f09b427 There's a bug in the repeated IO & mem copy speedups. I
added --enable-repeat-speedups with default to disabled.
Reconfigure/recompile and the speedup code will be #ifdef'd
out for now.  It manifested as junk written to the VGA screen
while booting/running Windows.

Also made some more mods to the main cpu loop.  Moved the
handling of EXT/errorno outside the main loop, much like
the extra EIP/ESP commits were moved, for a little better
performance.

I changed the fetch_ptr/bytesleft method of fetching to
a slightly different model, which calculates a window
for which EIP will be valid (land on the current page),
and a bias which when applied to EIP will be from
0..upper_page_limit.  Speed is about the same for either
method, but a pseudo-op/threaded-interpreter will plug
in better with this and be faster.
2002-09-02 18:44:35 +00:00
Kevin Lawton
3d8e5f8b61 Removed the BX_FETCHDECODE_CACHE mods, and the patch that
Bryce created for use of ensuring all mods were removed
cleanly.
2002-09-01 23:02:36 +00:00
Kevin Lawton
3a5f338419 Integrated patches for:
- Paging code rehash.  You must now use --enable-4meg-pages to
    use 4Meg pages, with the default of disabled, since we don't well
    support 4Meg pages yet.  Paging table walks model a real CPU
    more closely now, and I fixed some bugs in the old logic.
  - Segment check redundancy elimination.  After a segment is loaded,
    reads and writes are marked when a segment type check succeeds, and
    they are skipped thereafter, when possible.
  - Repeated IO and memory string copy acceleration.  Only some variants
    of instructions are available on all platforms, word and dword
    variants only on x86 for the moment due to alignment and endian issues.
    This is compiled in currently with no option - I should add a configure
    option.
  - Added a guest linear address to host TLB.  Actually, I just stick
    the host address (mem.vector[addr] address) in the upper 29 bits
    of the field 'combined_access' since they are unused.  Convenient
    for now.  I'm only storing page frame addresses.  This was the
    simplest for of such a TLB.  We can likely enhance this.  Also,
    I only accelerated the normal read/write routines in access.cc.
    Could also modify the read-modify-write versions too.  You must
    use --enable-guest2host-tlb, to try this out.  Currently speeds
    up Win95 boot time by about 3.5% for me.  More ground to cover...
  - Minor mods to CPUI/MOV_CdRd for CMOV.
  - Integrated enhancements from Volker to getHostMemAddr() for PCI
    being enabled.
2002-09-01 20:12:09 +00:00
Volker Ruppert
38666a2cfb - PCI memory handling moved to bx_mem_c
* shadow RAM array and fetch function are now a part of the memory code
  * removed unnecessary PCI macros and functions load_ROM() and mem_read()
2002-08-31 12:24:41 +00:00
Gregory Alexander
5d7c6627fd I botched the linked list implementation pretty badly.
Kudos to TLD for fixing it for me.
2002-06-06 23:03:09 +00:00
Gregory Alexander
1be5b1d46c Added a linked list to further speed up icache invalidates.
These should be pretty snappy now.  It's time to generate
some actual statistics.

 Modified Files:
 	cpu/cpu.cc cpu/cpu.h cpu/init.cc memory/memory.cc
2002-06-05 21:51:30 +00:00
Gregory Alexander
c41505e342 Added a RPN directory for the cache to help make invalidates
faster.  Hopefully this won't slow things down too much.

 	config.h.in cpu/cpu.cc cpu/cpu.h memory/memory.cc
2002-06-05 03:59:31 +00:00
Gregory Alexander
fda1b874e9 Check in FETCHDECODE Caching, with changes.
Specific changes from the patch:

1.) renamed fdcache_eip to fdcache_ip, as it is using
the RIP instead of the EIP.

2.) added a Boolean array fdcache_is32 which uses is32
to determine icache hits.  Otherwise we could run 32-bit
code as 16-bit or vice versa.


 Modified Files:
 	config.h.in cpu/cpu.cc cpu/cpu.h memory/memory.cc
2002-06-03 22:39:11 +00:00
Bryce Denney
30aaf4088e - commit patch.wxwindows.gz in the main branch. Now you can try out
the wxwindows interface by just "configure --with-wx; make"

  Modified Files:
    Makefile.in bochs.h config.h.in configure configure.in
    load32bitOShack.cc logio.cc main.cc cpu/cpu.cc cpu/cpu.h
    debug/dbg_main.cc gui/Makefile.in gui/control.cc gui/gui.cc
    gui/siminterface.cc gui/siminterface.h gui/x.cc iodev/cdrom.cc
    iodev/keyboard.cc memory/misc_mem.cc
  Added Files:
    README-wxWindows wxbochs.rc gui/wx.cc gui/wxmain.cc
    gui/wxmain.h gui/bitmaps/cdromd.xpm
    gui/bitmaps/configbutton.xpm gui/bitmaps/copy.xpm
    gui/bitmaps/floppya.xpm gui/bitmaps/floppyb.xpm
    gui/bitmaps/mouse.xpm gui/bitmaps/paste.xpm
    gui/bitmaps/power.xpm gui/bitmaps/reset.xpm
    gui/bitmaps/snapshot.xpm
  Removed Files:
    patches/patch.wxwindows.gz
2002-04-18 00:22:20 +00:00
instinc
748ccdef95 put bx_guard under #if/#endif BX_DEBUGGER 2002-04-01 13:14:37 +00:00
instinc
18c79cee9c check if CTRL+C is pressed while in a HLT instruction 2002-04-01 04:02:02 +00:00
Bryce Denney
0fef43eeb6 - in debugger, fix instruction tracing for SMP simulation. This was
fixed in patch.smp-instr-trace for Bochs 1.3, but the patch conflicted
  with the latest source.  It was simple enough to just make the changes by
  hand.  This should fix bug [ #532321 ] SMP debug: trace-on fails
2002-03-20 23:50:23 +00:00