Stanislav Shwartsman
2ab50c7d66
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
Stanislav Shwartsman
7cc9cffeed
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
Stanislav Shwartsman
1bf18b8aae
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
...
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
This enable better compiler optimizations and reduce binary size
2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
e15012cfcf
fix code duplication in <limiting max cpuid leaf to 0x02 for winnt> feature
2021-01-02 16:28:51 +00:00
Stanislav Shwartsman
c6050a99d1
implemented AVX encoded VNNI instructions published in recent SDM - not tested yet
2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
4023b640d6
Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS)
2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
b891789c3d
implemented (experimental) TSC Adjust MSR
2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
f90e5f4f44
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
...
Only missing items (to be added soon):
- Supervisor Shadow Stack EPT Control is not implemented yet
- SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
8c385f2a9a
fix in cpu features print
2019-12-06 11:05:05 +00:00
Stanislav Shwartsman
7861ff5160
fixed typo in feature name
2019-12-06 10:39:42 +00:00
Stanislav Shwartsman
0c75e0beaf
extract xcr0_support bits calculation to a function
2019-12-06 09:23:28 +00:00
Stanislav Shwartsman
893aa10359
cosmetic changes
2019-12-04 19:53:08 +00:00
Stanislav Shwartsman
d766cc8112
implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition
2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
2eb47f866f
added minor clarifications based on most recent AMD SDM published
2019-07-30 18:17:21 +00:00
Stanislav Shwartsman
4d10852c04
impemented recently published VP2INTERSECTD/Q instructions
2019-05-25 19:07:09 +00:00
Stanislav Shwartsman
0c28705b18
fixed compilation under MAC env
2019-05-18 04:50:07 +00:00
Stanislav Shwartsman
54bdb24e4b
remove MOVDIRI opcode extension for now until fugured out how nicely do MOVDIR64B, they better to be both done with same CPUID feature name
2019-02-22 19:15:53 +00:00
Stanislav Shwartsman
9bc7faf493
dump all supported CPU fetures into Bochs log from CPUID object
2019-01-05 20:17:39 +00:00
Stanislav Shwartsman
a8413aa838
update comments base on latest AMD spec
2018-05-27 18:13:24 +00:00
Stanislav Shwartsman
31d29734d6
some comments about more CPUID leaf 80000008.EBX by Ryzen
2017-03-28 19:11:42 +00:00
Stanislav Shwartsman
e5c64b3b56
cleanup of warning messages from cpuid code
2017-03-26 20:12:14 +00:00
Stanislav Shwartsman
411ea954b4
implemented CLZERO instruction from AMD Ryzen CPU
2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
ebbf8f9e0f
adjustments in AMD Ryzen CPUID
2017-03-15 22:14:10 +00:00
Stanislav Shwartsman
3a033fa6db
implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen)
2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
402e2cfad0
move cpuid warning messages to base cpuid class - reduce code cleanup
2017-03-13 19:59:48 +00:00
Stanislav Shwartsman
980eaa7937
move cpuid leaf 80000008 to base bx_cpuid_t class to remove code dupolication
2017-03-09 21:25:18 +00:00
Stanislav Shwartsman
bcb36e81fa
experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys
2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
be4b73c6d2
extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class
2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
9315742f3d
cleanups of vmcs mapping related stuff
2015-07-07 21:06:56 +00:00
Stanislav Shwartsman
5fe1423ab6
introducr new class for VMCS mapping so it can be customized per cpuid
2015-07-06 18:46:57 +00:00
Stanislav Shwartsman
080ceb8293
don't crash when running on 386 with no FPU model
2015-03-27 21:39:24 +00:00
Stanislav Shwartsman
b60d7d3154
Cleanup of CPUDB modules, moved common functionality into bx_cpuid_t base class
...
Added Pentium (P54C) AKA Pentium with no MMX to CPUDB
2015-02-11 21:31:17 +00:00
Stanislav Shwartsman
03dab0b0c9
remove debug prints from param tree dump in xml format, small code reorg
2014-11-30 21:26:33 +00:00
Stanislav Shwartsman
5f4e7f8b49
fixed compilation when APIC if snot enabled
2014-11-01 10:25:42 +00:00
Stanislav Shwartsman
caab07e580
move common code (extended topology leaf) into base cpuid class to save code duplication
2014-10-15 14:25:08 +00:00
Stanislav Shwartsman
f8267ec3a7
rework in CPUID code (fixed code duplication). Re-enable perfmon reporting in CPUID because Win8/Win10 installation doesn't want to start without perfmon reported. TODO: implement basic perfmon support (at least only fixed counters) because win7-64 doesn't install with perfmon reported but not implemented
2014-10-15 08:04:38 +00:00
Stanislav Shwartsman
78327d3e5e
First step toward completely configurable CPU.
...
Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
...
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
8399dee24c
implemented AVX float16 convert instructions
2011-06-11 13:12:32 +00:00
Stanislav Shwartsman
77e15511be
AVX2 and BMI instructions were published on http://software.intel.com/en-us/avx
2011-06-10 08:46:10 +00:00
Stanislav Shwartsman
04e9254e2c
AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A
2011-05-30 20:15:50 +00:00
Stanislav Shwartsman
1ba77b9f10
fixed defined but not used warnings
2011-05-29 20:42:47 +00:00
Stanislav Shwartsman
5748c6b9f5
first fix for SMEP
2011-05-29 18:08:37 +00:00
Stanislav Shwartsman
ee3f9e36cb
Implemented Supervisor Mode Execution Protection (SMEP)
2011-05-29 16:28:26 +00:00
Stanislav Shwartsman
6ace540891
update for rev39 of Intel SDM
2011-05-28 20:20:25 +00:00
Stanislav Shwartsman
e0160b4f29
ability to turn on/off AVX if compiled in
2011-05-24 20:33:36 +00:00
Stanislav Shwartsman
de95fa8e13
more changes towards configurable cpuid
2011-05-24 18:23:28 +00:00
Stanislav Shwartsman
610df62e93
fixed segfault with x86-64 disabled
2011-04-22 17:56:27 +00:00
Stanislav Shwartsman
fb360ac334
bugfix
2011-04-22 07:39:38 +00:00
Stanislav Shwartsman
024a1ace38
move X2APIC to be .bochsrc option, rework of the cpuid code
2011-04-21 13:27:42 +00:00
