Commit Graph

38 Commits

Author SHA1 Message Date
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet)
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions.
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
6751af5d8e added AVX FMA extensions support. The implementation is based on QEMU patch by Peter Maydell (fixed) 2011-09-29 22:20:56 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
fefa4d5e5b added PIII Katmai to CPUDB 2011-07-30 14:30:35 +00:00
Stanislav Shwartsman
e48765a511 VMX fixed, cleanups 2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
04e9254e2c AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A 2011-05-30 20:15:50 +00:00
Volker Ruppert
c78026a9a2 - deleted executable properties from source files 2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support
many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
f9f868247a split more SSE ops 2010-12-30 20:35:10 +00:00
Stanislav Shwartsman
dd6cc5ce42 update todo 2010-04-08 20:08:05 +00:00
Stanislav Shwartsman
79466dffe2 apic virtualization + vmx fixes 2010-03-16 14:51:20 +00:00
Stanislav Shwartsman
d9f701ddb0 LSL/LAR fixed in 64-bit mode 2009-10-02 16:09:08 +00:00
Stanislav Shwartsman
1b72e66bb3 support for apic global disable
separate between I/O apic and local apic
2009-02-18 22:25:04 +00:00
Stanislav Shwartsman
82969504d8 updated CPU TODO 2009-01-31 11:34:51 +00:00
Stanislav Shwartsman
69bd21bf1d 1G pages support for CPU 2008-12-11 21:00:01 +00:00
Stanislav Shwartsman
7494b8823b - Support of AES CPU extensions, to enable configure with
--enable-aes option
2008-05-30 20:35:08 +00:00
Stanislav Shwartsman
4f3f8608f7 Fixed MASKMOVDQU instruction decoding 2008-04-16 05:41:43 +00:00
Stanislav Shwartsman
730214a8ec Add TODO items 2008-04-08 17:59:51 +00:00
Stanislav Shwartsman
52770feedd Add CPUID bits comments and update CPU TODO 2008-04-04 12:23:19 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
05a5923971 Merged Bochs instrumentation patch by Lluis Vilanova 2007-12-13 17:16:21 +00:00
Stanislav Shwartsman
b90e97858b Update CPU TODO and CHANGES 2007-11-01 19:04:01 +00:00
Stanislav Shwartsman
8adbbcf17c Started first implementation of MONITOR/MWAIT 2007-10-11 21:29:01 +00:00
Stanislav Shwartsman
82b7eaabd5 CLFLUSH do not fault when checking execute only segment 2007-10-10 21:48:46 +00:00
Stanislav Shwartsman
2548c05537 Enable SSE4_2 in CPUID 2007-10-01 21:08:26 +00:00
Stanislav Shwartsman
91e6ca8d5c Implemented MTRR support
Fixes in #PF exception priority
2007-09-20 17:33:35 +00:00
Stanislav Shwartsman
895891b673 Implemented #AC check under configure option
Fixes in misaligned SSE support
2007-07-31 20:25:52 +00:00
Stanislav Shwartsman
e26609fa97 Support for Intel LSS/LFS/LGS in 64-bit mode
TODO: have both AMD and Intelk versions
2007-04-09 20:28:15 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction
Set of minor fixes for correctness
2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
d7d2de421f Remove code duplication in CPU and memory objects initialization 2006-01-11 18:22:12 +00:00
Stanislav Shwartsman
393a653fb4 Fix typo 2006-01-05 21:40:07 +00:00
Stanislav Shwartsman
82dcab043f Update TODO 2005-11-21 21:15:35 +00:00
Stanislav Shwartsman
0c6a401f30 Update CPU/TODO 2005-11-09 18:07:49 +00:00
Stanislav Shwartsman
ab81296e33 Update CHANGES/TODO
Change BX_INFO to BX_DEBUG in read CR4 function
2005-10-23 21:11:32 +00:00
Stanislav Shwartsman
51347f2604 PAUSE instruction still should be implemented ... 2005-10-13 22:53:03 +00:00
Stanislav Shwartsman
734cc8496f Update changes and cpu/todo 2005-09-05 17:50:37 +00:00
Stanislav Shwartsman
5b258fd453 Add todo file to CPU 2005-08-10 19:04:19 +00:00