Commit Graph

442 Commits

Author SHA1 Message Date
Stanislav Shwartsman
fc6671a67b Commented out assertion which doesn't work 2008-06-16 04:49:19 +00:00
Stanislav Shwartsman
9d1bc903d8 Fixed typo in MTRR, added assertions 2008-06-15 20:41:34 +00:00
Stanislav Shwartsman
a0e66d0e4c fixed variable name 2008-06-14 16:55:45 +00:00
Stanislav Shwartsman
92568f7525 Faster 32-bit emulation wwith 64-bit enabled mode.
~10% speedup byu optimization of 32-bit mem access
2008-06-12 19:14:40 +00:00
Stanislav Shwartsman
3d3dba7804 - Implemented GD bit in DR7 register 2008-06-02 19:50:40 +00:00
Stanislav Shwartsman
b7480b3e6f - Fixed x86 data breakpoint match when breakpoint length is 8 bytes
- FIxed x86 data breakpoint in paging disabled mode
2008-06-02 18:41:08 +00:00
Stanislav Shwartsman
d2ba79abdd Removed PANIC in DqRq function 2008-05-31 21:17:02 +00:00
Stanislav Shwartsman
764756d74a Handle reserved bits of CR8 2008-05-31 09:26:28 +00:00
Stanislav Shwartsman
d295371450 - Correctly handle segment a byte in BIG real mode 2008-05-26 21:46:39 +00:00
Stanislav Shwartsman
3619c0f6b4 Some changes to make x86-debugger feature working back 2008-05-23 17:49:46 +00:00
Stanislav Shwartsman
8118ba1a67 Fixed debug extensions exception priority 2008-05-19 19:59:29 +00:00
Stanislav Shwartsman
bef3450baa Fixes to 64-bit mode 2008-05-11 20:46:11 +00:00
Stanislav Shwartsman
4a76bd2169 Fixed setting of reserved bits in CR3 register 2008-05-11 19:36:06 +00:00
Stanislav Shwartsman
ec1ff39a5f Splitted memory access methods for 32 and 64-bit code.
The 64-bit code got >10% speedup, the 32-bit code also got about 2% because laddr cacluation optimization
2008-05-10 18:10:53 +00:00
Stanislav Shwartsman
3634c6f892 Compress FPU tag word 2008-05-10 13:34:47 +00:00
Stanislav Shwartsman
6ebae41ad7 print physcial address with special format - preparations for 64-bit physical address emu 2008-05-09 22:33:37 +00:00
Stanislav Shwartsman
80c9b5fcbe Compilation error fixed 2008-05-09 08:28:00 +00:00
Stanislav Shwartsman
eedf26627f Fixes in CMPXHG8B instruction - slight speedup and correct #AC check 2008-05-05 21:48:07 +00:00
Stanislav Shwartsman
64a80c8a2d - Added canonical check for SYSENTER MSRs in WRMSR
- Fixed LLDT and LTR instructions in 64-bit mode
- Fixed error code for not 64-bit CS in interrupt from long mode
2008-05-04 21:25:16 +00:00
Stanislav Shwartsman
50c9674d2e Small optimization in memory access functions 2008-05-03 17:33:30 +00:00
Stanislav Shwartsman
06c6ac0060 - Fixed effective address wrap in 64-bit mode with 32-bit address size
- Fixed SMSW instruction in 32-bit and 64-bit modes
2008-04-28 18:18:08 +00:00
Stanislav Shwartsman
67e534832b Remove from CPU reference to MEM object - it is only one and could be static 2008-04-27 19:49:02 +00:00
Stanislav Shwartsman
9047c9be96 Support for reserved bits checking in paging
Check for page is in DTLB before invalidating by INVLPG
2008-04-25 20:08:23 +00:00
Stanislav Shwartsman
a647c7e551 Check for old TSS limits in task switching logic
MSR_GSKERNELBASE should be canonical - added WRMSR check
2008-04-25 11:39:51 +00:00
Stanislav Shwartsman
24f1507fa9 - sysenter/exit should be supported in v8086 mode as well
- fixed missed CS.LIMIT check in all far calls/jmps in real/v8086 mode
2008-04-20 21:44:13 +00:00
Stanislav Shwartsman
280617288c Mode change in SYSENTER/EXIT/CALL/RET could happen only when already in long mode 2008-04-20 18:17:14 +00:00
Stanislav Shwartsman
a91ef4e31b Ignore CS.L bit when EFER.LMA is not set
Add potentially missed CPU mode change in SYSCALL/RET/ENTER/EXIT
2008-04-20 18:10:32 +00:00
Stanislav Shwartsman
d9bf2b8453 Small emulation speed optimization 2008-04-19 22:29:44 +00:00
Stanislav Shwartsman
15e9dca062 - support 64-bit write to MSR_TSC using WRMSR instruction
- fixed save/restore param type for async_event
- fixed setting of reserved bits in upper part of CR4 in 64-bit mode
2008-04-18 18:32:40 +00:00
Stanislav Shwartsman
892fa99c6f - prefetch hint should be NOP when use in register mode
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
  even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
67f02bfa12 Add debugger callback 2008-04-15 21:29:18 +00:00
Stanislav Shwartsman
fab4042cad SYSENTER/SYSEXIT in long mode 2008-04-15 14:41:50 +00:00
Stanislav Shwartsman
a851cfd8f0 Re-implemented modebp debugger function in simple and more clean way 2008-04-07 19:59:53 +00:00
Stanislav Shwartsman
fea49bb270 Fixed linear address wrap in legacy (not long64) mode 2008-04-07 18:39:17 +00:00
Stanislav Shwartsman
5826e2843a Inline pop/push functions
Store only single byte of opcode in b1() - speedup shift instructions
Code cleanups
2008-04-05 17:51:55 +00:00
Stanislav Shwartsman
41fe0b3ebb Fix code duplication 2008-04-03 18:59:10 +00:00
Stanislav Shwartsman
e91409704f Convert EFER to val32 register, similar to other control registers 2008-03-31 20:56:27 +00:00
Stanislav Shwartsman
a22160959b HLT callback to Bochs internal debugger 2008-03-23 21:39:01 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
a459a64f3e whispace, tab2space, indent, dos2unix and other cleanups 2008-02-15 22:05:43 +00:00
Stanislav Shwartsman
cdcd7522aa Added RIP to the GPR register file as lst register
This allowed to optimize (read - remove) two more BxResolve methods in 64-bit mode
+ Some white space cleanup
2008-02-15 19:03:54 +00:00
Stanislav Shwartsman
8615022962 Added first stubs for XSAVE/XRESTOR implementation
Disassemble XSAVE/XRSTOR instructions (4 instructions)
Update CHANGES - a bit speculatively
2008-02-12 22:41:39 +00:00
Stanislav Shwartsman
8d7410a852 Canonical check have higher priority than #AC check 2008-02-11 20:52:10 +00:00
Stanislav Shwartsman
965568ea88 cleanups 2008-02-07 18:28:50 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
032b13047c Minor fix in cpu reset, bug sometimes caused to run on garbage memory after software reset. Some small debug messages fixes 2008-02-01 13:25:23 +00:00
Stanislav Shwartsman
d18b90484f Added instr callbacks for sysenter/sysexit/syscall/sysret 2008-01-18 08:57:35 +00:00
Stanislav Shwartsman
e287dcd91a correctly implement CLFLUSH protection/paging checks + add instrumentation callback 2008-01-16 22:56:17 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
838fb2a048 Fixing V2008 warnings - they found a bug in sse_pfp.cc ! 2007-12-23 17:21:28 +00:00
Stanislav Shwartsman
5d4e32b8da Avoid pointer params for every read_virtual_* except 16-byte SSE and 10-byte x87 reads 2007-12-20 20:58:38 +00:00
Stanislav Shwartsman
b516589e4e Changes in write_virtual_* and pop_* functions -> avoid moving parameteres by pointer 2007-12-20 18:29:42 +00:00
Stanislav Shwartsman
46366b5064 Speedup simulation by eliminating CPL==3 check from read/write_virtual* functions 2007-12-16 21:03:46 +00:00
Stanislav Shwartsman
d9a59c7a1f Added ability to merge traces cross JCC branch instructions
Makes traces longer -> emulation faster in average
2007-12-14 20:41:09 +00:00
Stanislav Shwartsman
db69a25c36 Trace cache instrumentation methods
Next step will be tracing cross non-taken branches
2007-12-14 11:27:44 +00:00
Stanislav Shwartsman
48d815427c According to AMD docs INVLD/WBINVLD instructions not required to flush TLBs 2007-12-14 10:15:12 +00:00
Stanislav Shwartsman
85d10e4f72 Added MWAIT callback 2007-12-13 21:41:32 +00:00
Stanislav Shwartsman
91e0db63c4 no need to invalidate prefetch queue for RDMSR/WRMSR 2007-12-03 21:43:14 +00:00
Stanislav Shwartsman
c58e95f611 Make hw breakpoint match check a function - normally it should be called from read/write_virtual as well 2007-12-03 20:49:24 +00:00
Stanislav Shwartsman
8cfd17202a some simple SSE code optimizations 2007-11-27 22:12:45 +00:00
Stanislav Shwartsman
48650a70b4 Optimized alignment check 2007-11-20 21:22:03 +00:00
Stanislav Shwartsman
e1496bb9e0 Small optimization 2007-11-18 18:40:38 +00:00
Stanislav Shwartsman
d9e58bd598 split11b on opcode tables level - split almost eevery splittable instruction
will be continued
2007-11-17 12:44:10 +00:00
Stanislav Shwartsman
24e1936fbb Fixed compilation warning when compiling with no x86-64 2007-11-09 12:06:34 +00:00
Stanislav Shwartsman
5a172541e2 Small cleanup 2007-11-01 20:43:53 +00:00
Stanislav Shwartsman
e137560b14 Complete MONITOR/MWAIT implemntation (including monitoring of memory range)
Fixed PANIC in read/write Cr/Dr - should #UD with unkown register used
2007-11-01 18:03:48 +00:00
Stanislav Shwartsman
4ec7f5df39 Optimize access to IP (16 bit) - made IP register similar to GPR 2007-10-18 22:44:39 +00:00
Stanislav Shwartsman
082eb05b6b First step to fully configurable CPUID
- put CPUID functions data into array, in future we could load this array from configure file
 - cpuid initialize function is more flexible now but still reuire some work
2007-10-12 19:30:51 +00:00
Stanislav Shwartsman
8adbbcf17c Started first implementation of MONITOR/MWAIT 2007-10-11 21:29:01 +00:00
Stanislav Shwartsman
f6ed95785f added cpu state param - for future use and for dbg info
started to move debugger to info bx_param interface -> info sse and info mmx commands modified
2007-10-11 18:12:00 +00:00
Stanislav Shwartsman
82b7eaabd5 CLFLUSH do not fault when checking execute only segment 2007-10-10 21:48:46 +00:00
Stanislav Shwartsman
071c5c1a26 A lot of changes but everything is really trivial.
Make save/restore default feature, the configure option for save/restore removed from configure script and save/restore made available forever. All code now assume it is exists. Bochs save/restore tree previosly called "save_restore" renamed to "bochs" tree and it will be havily used everywhere, starting from save/restore and ending by various bochs debugger functions. I am going to rework debugger code to get rid of debug CPU access functions and use this "bochs" param tree instead
2007-09-28 19:52:08 +00:00
Stanislav Shwartsman
e812f81e7b Fixes in zero upper ECX 2007-09-25 16:11:32 +00:00
Stanislav Shwartsman
91e6ca8d5c Implemented MTRR support
Fixes in #PF exception priority
2007-09-20 17:33:35 +00:00
Stanislav Shwartsman
70f513b07b Make efer control MSR separate register 2007-09-10 20:47:08 +00:00
Stanislav Shwartsman
895891b673 Implemented #AC check under configure option
Fixes in misaligned SSE support
2007-07-31 20:25:52 +00:00
Stanislav Shwartsman
38d1f39c77 Converted CR0 bits to one register similar to CR4 - a bit slower but helps with other features implemntation 2007-07-09 15:16:14 +00:00
Stanislav Shwartsman
7c6c2bb520 Removed PANIC message 2007-06-08 09:25:30 +00:00
Stanislav Shwartsman
65a99eb736 Change BX_ERROR to BX_DEBUG 2007-04-25 20:14:15 +00:00
Stanislav Shwartsman
6c139a9c8c Define LIN and PHY address size in config.h 2007-04-14 10:05:30 +00:00
Stanislav Shwartsman
d3252fbc1c Removed unneeded invalidate_prefetch_q from RDMSR instruction 2007-02-23 22:08:43 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction
Set of minor fixes for correctness
2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
6c63e84d23 Fixed CR3 masking in long mode
Added PANIC assertion of 32-bit physical address in PAE mode
cleanup
2006-10-04 19:08:40 +00:00
Stanislav Shwartsman
02c2fc9e89 Fixed priveledge level checks 2006-09-10 16:56:55 +00:00
Stanislav Shwartsman
fdac9efa9b Fixed ton of code duplication.
Do not save/restore XMM8-XMM15 not in 64-bit mode
2006-08-31 18:18:17 +00:00
Stanislav Shwartsman
65082e4a4f Handle granularity field for LDT
Next step - fix code duplication with TSS
2006-08-25 19:56:03 +00:00
Stanislav Shwartsman
3ce7764fce Fixes in 64-bit decoding 2006-08-11 17:23:36 +00:00
Stanislav Shwartsman
45353d5e6f Fixed DR registers handling in x86-64 mode 2006-06-26 21:07:44 +00:00
Stanislav Shwartsman
9269288319 Fix SR macros mis-use. Need to add assertion into bxlist_c and check that it has no 2 params with same name inside ! 2006-06-14 16:44:33 +00:00
Stanislav Shwartsman
49d7b4614f Fixed another bug generator - duplication between descriptor type field and four descriptor cache bits 2006-06-12 16:58:27 +00:00
Stanislav Shwartsman
308521e7ce Fixes in SYSCALL/SYSRET instructions
Use parse_selector to avoid code duplication
2006-06-11 21:37:22 +00:00
Stanislav Shwartsman
6c3420a18b Add debug prints before any #GP excepion which only possible to be generated 2006-06-09 22:29:07 +00:00
Stanislav Shwartsman
8b55085c76 Merge tss286 and tss386 segment descriptor cache fields to one structure 2006-05-21 20:41:48 +00:00
Stanislav Shwartsman
f4c7b4074e Support for x86-64 in x86 debugger (DR0-DR7) 2006-05-13 12:49:45 +00:00
Stanislav Shwartsman
9a32d0e98f Optimize debug registers handling 2006-05-13 12:29:12 +00:00
Stanislav Shwartsman
63dc4d4e10 Fixed CR4 GP(0) condition (patch by no_mayl in mailing list) 2006-04-23 16:11:16 +00:00
Stanislav Shwartsman
d972e4a4b7 Fixed CR3 restore in RSM instruction
Added HALT state indication (actually make existant one working for single CPU)
2006-04-10 19:05:21 +00:00
Stanislav Shwartsman
45f30f0a4c some code written to enter CPU to shutdown state.
finally the shutdown handling should be done exactly as in VmWare - the GUI should ask user if the CPU should reset and go to HLT/IF=0 if user choosed to stay in shutdown mode.
CPU configure option reset-on-triple-failt should be extended to shutdown-reset=0|1
small code cleanups and fixes
2006-04-07 20:47:32 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash:
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
da3d26d7f4 Preliminary implemntation of SMM save statei
Fixed fetchModeMask for load32bitOsStack
2006-03-27 18:02:07 +00:00
Stanislav Shwartsman
f347ab97bf Fixed CALL/JMP far through call gate 64
Decode SWAPGS and RDTSCP instructions
Indent changes in fetchdecode
2006-03-22 20:47:11 +00:00
Stanislav Shwartsman
a64b16391d Remove unused vars 2006-03-15 17:57:11 +00:00
Stanislav Shwartsman
e85a90a720 Remove cpu.h -> devices.cc dependancy, kill_bochs_request moved from CPU to bx_pc_system
Small Icache simplification and speedup
2006-03-14 18:11:22 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
324d75e749 Fix another broking change 2006-03-04 09:22:55 +00:00
Stanislav Shwartsman
5fad793989 move local apic handling to the access_linear function for the memory class.
speedup the whole simulation by 2% !
2006-03-01 22:32:24 +00:00
Stanislav Shwartsman
a527b2cfca first smm - implement cpu state when switching to SMM
smm coming soon
fixed code duplication in init.cc
2006-02-28 19:50:08 +00:00
Stanislav Shwartsman
55ceecf79b Small optimization in icache page-write-stamp 2006-02-28 17:47:33 +00:00
Stanislav Shwartsman
024ce249bf Define SMM mode for future implementation.
I would like all next commits be aware of SMM mode.
It can't be implemented right now (too many questions w/o answers) but it will be done till next major release definitelly.
2006-02-14 19:00:08 +00:00
Stanislav Shwartsman
9b451f43e2 Save/restore RIP/RSP only on FAULT type exceptions, not on traps 2006-02-11 09:08:02 +00:00
Stanislav Shwartsman
9a15f59e05 Fixed bug in SYSRET legacy mode 2006-02-02 17:55:48 +00:00
Stanislav Shwartsman
9df8079206 Write to MSR_TSC implemented (patch by Bryce) 2006-01-21 12:06:03 +00:00
Stanislav Shwartsman
7bf51e48db Print FS_MSR_BASE and GS_MSR_BASE to debug registers dump (requested in bug report [ 1406387 ] JMP instruction should display absolute address)
Fixed fetch mode mask initialization (bug report 1400027  Boundary instruction cache error for uninitialized memory)
For safety only - everytime when changing CS register update fetch mode mask.
Actually it need to be updated everytime when there is a chance for execute mode change or 16/32 bit mode change.
2006-01-16 19:22:28 +00:00
Stanislav Shwartsman
a74b63eb3d Allow writing PCE to CR4 2006-01-13 11:11:29 +00:00
Stanislav Shwartsman
393a653fb4 Fix typo 2006-01-05 21:40:07 +00:00
Stanislav Shwartsman
70cc5a7fb0 Fix incorrect commit 2005-12-12 19:54:48 +00:00
Stanislav Shwartsman
f863d1e902 Generate #GP exception instead of #TS when TSS selector points to bad TSS 2005-12-12 19:44:06 +00:00
Stanislav Shwartsman
fe02ecab65 Do not flood log with WBINVD/INVD messages 2005-11-27 18:36:19 +00:00
Stanislav Shwartsman
8c91790680 Redefine registers accessors in cpu.h
Change BxSupportPAE and BxSupportGlobalPages macros to Bochs style names
Set bx_cpu_id in BX_CPU_C constructor (safe way)
Backup cpu-level check for paging features at compile time (already checked in configure)
Some warnings and indent fixes
speed up get_segment_base method for x86-64 case
2005-11-26 21:36:51 +00:00
Stanislav Shwartsman
9314752bb1 Rewritten task_switch mechnism according to AMD docs
This should fix the #SF bug report
736279  Jump to Task
2005-11-21 21:10:59 +00:00
Stanislav Shwartsman
cd2a9f317d Do not PANIC when HLT with IF=0, only BX_INFO 2005-11-04 15:15:02 +00:00
Stanislav Shwartsman
ab81296e33 Update CHANGES/TODO
Change BX_INFO to BX_DEBUG in read CR4 function
2005-10-23 21:11:32 +00:00
Stanislav Shwartsman
64ba97210b INVD/WBINVD should flush caches and TLB 2005-10-18 18:07:52 +00:00
Stanislav Shwartsman
670395f1be VME support - beta #1 2005-10-17 13:06:09 +00:00
Stanislav Shwartsman
e83c77db49 Preparing to VME implementation
DO NOT ENABLE VME option until the implementation will be completed !
2005-10-16 23:13:19 +00:00
Stanislav Shwartsman
469358aaf9 Move SHOW_IPS action to bx_gui object, may be some GUI will be able to print IPS online in the simulation window status bar ...
Small code cleanup
2005-10-13 16:22:21 +00:00
Stanislav Shwartsman
39fc11c5da Fix compilation error 2005-10-09 18:32:36 +00:00
Stanislav Shwartsman
7869ab425f LTR should #GP when loading NULL selector
fixed check for SYSENTER/SYSEXIT instructions
according to new Intel references
2005-10-01 07:47:00 +00:00
Stanislav Shwartsman
8c783bc329 Fixed cpu_mode corruption in x86-64 mode
Removed all potentially unsafe and duplicated code in setFLAGS methods to avoid such kind of problems in future
2005-09-29 17:32:32 +00:00
Stanislav Shwartsman
6096698393 Fixed CLTS and HLT GP0 check 2005-09-14 20:01:42 +00:00
Stanislav Shwartsman
8be190d848 Implemented RDTSCP instruction 2005-08-05 12:47:33 +00:00
Stanislav Shwartsman
954aae3f99 Speedup push/pop operations, they actually not needed to do can_push/can_pop checkes, the same checkes already done in read/write_virtial methods
Split push_seg_reg methods according to op size
2005-07-31 17:57:27 +00:00
Stanislav Shwartsman
5da36b7d3d Fixed code duplication, added canonical address checking for RETF in long mode 2005-07-29 06:29:57 +00:00
Stanislav Shwartsman
4638f09b24 Added BX_INSTR_HLT instrumentation callback 2005-07-07 18:40:35 +00:00
Stanislav Shwartsman
3d2e2162f3 Code indent, no functionality changes 2005-07-01 14:06:02 +00:00
Stanislav Shwartsman
015ad92958 Added SMP status to TODO file
Removed abusive BX_INFO from WBINVD instruction
The PREFETCHW (3DNow!) instruction should not #UD in x86-64 even on Intel w/o 3DNow!
2005-05-27 01:53:38 +00:00
Stanislav Shwartsman
6c318bd047 SFENCE/MFENCE/LFENCE methods not defined in CPU class and they NOP in fetchdecode.cc 2005-05-18 05:05:40 +00:00
Kevin Lawton
f829c9cf93 Typo in CR8 handling in MOV_CqRq/MOV_RqCq had a typo. A switch
target of 7 was used instead of 8.
2005-05-17 22:22:35 +00:00
Stanislav Shwartsman
494af8b1f3 Fixed segmentation fault for 2CPU cfg 2005-04-26 19:19:58 +00:00
Stanislav Shwartsman
501cca67c2 Fix compilation err 2005-04-18 17:41:15 +00:00
Stanislav Shwartsman
8482511af3 Fix compilation errors
Add BX_INFO for writing to TSC_MSR (not implemented message)
2005-04-18 17:21:34 +00:00
Stanislav Shwartsman
0f7f728e86 Added debug messages for interrupt function in long mode
Added mode switch debug prints
2005-03-30 20:53:04 +00:00
Stanislav Shwartsman
e6e9dd3825 Extend Bochs instrumentation
Compatability fixes
2005-03-17 20:50:57 +00:00
Stanislav Shwartsman
6e53a54907 Extend cpu_mode for :
#define BX_MODE_IA32_REAL       0x0   // CR0.PE=0
#define BX_MODE_IA32_PROTECTED  0x1   // CR0.PE=1, EFLAGS.VM=0
#define BX_MODE_IA32_V8086      0x2   // CR0.PE=1, EFLAGS.VM=1
#define BX_MODE_LONG_COMPAT     0x3   // EFER.LMA = 0, EFER.LME = 1
#define BX_MODE_LONG_64         0x4   // EFER.LMA = 1, EFER.LME = 1
2005-03-15 19:00:04 +00:00
Stanislav Shwartsman
c30e89289b Fixed R/O pages access in CPL=3 (TLB accessBits bug) 2005-03-03 20:24:52 +00:00
Stanislav Shwartsman
c583a6f9cf move segments and descriptors definitions and macroses for new descriptor.h 2005-02-27 17:41:45 +00:00
Stanislav Shwartsman
6e773a652a Fix SYSENTER/SYSEXIT instructions 2005-02-26 12:00:22 +00:00
Stanislav Shwartsman
830ca51b91 Merge patches:
1149720 critical - fix x86-64 SYSCALL RFLAGS masking
 1149758 wrmsr efer fix
2005-02-23 18:00:07 +00:00
Stanislav Shwartsman
2bfc842c09 CPU fixes by Kevin Lawton 2005-02-16 21:27:21 +00:00
Stanislav Shwartsman
5701f62a42 Fix compiler warnings with -wall 2005-02-03 18:43:23 +00:00
Stanislav Shwartsman
d27e81bdac -in case of --enable-ignore-bad-msr enabled read ignored MSRs as zeRo
- enabled #DE and #TSD and #MCE bits in CR4 register, previosly setting
    of one of these bits generated #GP(0) (Stanislav, Volker Ruppert)
2005-02-03 18:25:10 +00:00
Stanislav Shwartsman
7eb2f0aa3e Enable TSD in CR4 (RDTSC instruction is already implemented so it has no problem to enable TSD for CPU LEVEL >=5) 2005-01-23 21:13:49 +00:00
Stanislav Shwartsman
3cd646004f Fixed bug "1101168 APIC base address change" 2005-01-13 19:03:40 +00:00
Volker Ruppert
48ebc288c6 - MCE is supported on Pentium or higher (exception 18 never appears in Bochs) 2005-01-09 08:14:15 +00:00
Stanislav Shwartsman
5955549a8d Fixed bug report [#879050]
Bochs reports enabled APIC without support
2004-12-14 20:41:55 +00:00
Stanislav Shwartsman
730b8c0243 Fix this pointers in the code 2004-11-14 21:25:42 +00:00
Stanislav Shwartsman
1a6656ce91 Fixed compilation warnings (g++, -Wall)
Improve speed and precision of FPATAN FPU instruction
2004-11-04 22:41:24 +00:00
Stanislav Shwartsman
f06c8b6b95 EIP > CS.limit should not be a problem
Manual says that GP(0) shouldd be generated in this case ALWAYS
Fixed instructions PANIC messages to ERROR for this case
And ... do not leave PANIC messages w/o taking care that user could push CONTINUE button and program should know to continue after the PANIC code line. Mainly in rerurn instructions were several problems ...
2004-11-02 16:10:02 +00:00
Stanislav Shwartsman
80ee150d83 Imlemented CR8 register for X86-64 mode 2004-10-13 20:58:16 +00:00
Stanislav Shwartsman
4988a098f5 Small optimizations 2004-10-03 21:52:10 +00:00
Stanislav Shwartsman
040be015d8 1. Added required GP(0) exception when setting conficting flags in CR0
2. APIC disabled compilation error fixed
2004-09-21 20:19:19 +00:00
Stanislav Shwartsman
5c5b556f24 Merge softfloat-fpu-implementation_ver4_branch branch 2004-06-18 14:11:11 +00:00
Stanislav Shwartsman
e6991f043f pply patch
[ 924428 ] ET bit mismatch between CR0 and MSW
2004-06-03 17:57:29 +00:00
Stanislav Shwartsman
3274e0dd12 Commit patch
[ 950905 ] Do not PANIC on rare, bad input from user-mode
by h.johansson
with little changes and fixes
2004-05-10 21:05:51 +00:00
Stanislav Shwartsman
cdb68ff8c8 Reverting back the changes in data_xfer16.cc
Add/Fix bx_info messages in proc_ctrl.cc
2003-11-13 21:57:13 +00:00
Stanislav Shwartsman
d51aece0c1 Change BX_PANIC messages to BX_INFO when behaviour is accepted with Intel/AMD docs.
Instructions MOV_CxRx and MOV_RxCx are not supported in v8086 mode according to Intel manuals.
Also these instructions are treated as register-to-register regardless to MODRM byte fields (according to AMD manuals)
Also commit fix for MOV_EwSw by Kevin
2003-11-13 21:17:31 +00:00
Stanislav Shwartsman
ac20b6405a - FXSAVE/FXRSTOR instructions should be available in P6 mode
- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
789db2603e Added P4 support to CPUID instruction
Extracted CPUIS instructions to separate file
2003-09-26 15:32:41 +00:00
Stanislav Shwartsman
7f570b0150 Added PNI new streaming extensions instructions
PNI could be enabled by setting BX_SUPPORT_PNI in config.h
After the feature will be fully validation I'll also add configure option.

The implemntation is ~complete. I've missed only three FPU new opcodes of FUSTTP instruction and MONITOR/WAIT instructions.

Enjoy ! ;)
2003-08-29 21:20:52 +00:00
Stanislav Shwartsman
549eb70324 Committed CPU fixes from Vitaly Vorobyov:
[x] fixed bug in int01 (opcode 0xF1) emulation
[x] fixed bug in x86 debugger with dr0-dr3 registers

Committed disassembler bugfix from Dirk Thierbach:

[x] fixed bug in relative addresses in Jmp, Jcc, Call and so on
2003-08-03 16:44:53 +00:00
Stanislav Shwartsman
96984cb6cb Added missed fetchdecode table entry for SYSENTER/SYSEXIT 2003-06-20 08:58:12 +00:00
Stanislav Shwartsman
1d45167e5b Merged NEW-INSTRUCTIONS branch 2003-05-15 16:41:17 +00:00
Kevin Lawton
a17d06abcb Optimized the main cpu loop iCache checks to remove a redundant
check.

Commented out a number of instances of invalidate_prefetch_q(),
for branches which do not change CS since the EIP window mechanism
takes care of validating that EIP lands in the current page or not
in the main cpu loop anyways.

Fixed a couple cases (v8086 mode and real mode) of loading CS where
the EIP page window was not invalidated in segment_ctrl_pro.cc.
That may fix some aliasing problems reported before (OS2).
2003-05-10 22:25:55 +00:00
Volker Ruppert
79b811f23f - fixed warnings in these files:
cpu/fetchdecode.cc
  cpu/mmx.cc
  cpu/proc_ctrl.cc
  iodev/virt_timer.cc
  plugin.cc
2003-05-02 12:22:48 +00:00
Stanislav Shwartsman
cdfc3cbce4 instrumentation enchancements:
* renamed CPU_ID to BX_CPU_ID.
  with this new name there is no possibility for name contentions and BX_CPU_ID
  definition could be moved out to NEED_CPU_REG_SHORTCUTS block

* returned back `unsigned BX_CPU::which_cpu(void)` function

* added BX_CPU_ID parameter for
	BX_INSTR_PHY_READ(a20addr, len);
	BX_INSTR_PHY_WRITE(a20addr, len);
    now it will be
	BX_INSTR_PHY_READ(cpu_id, a20addr, len);
	BX_INSTR_PHY_WRITE(cpu_id, a20addr, len);
2003-02-13 15:04:11 +00:00
Stanislav Shwartsman
e1b8e5b9f9 Fixed FTW save/restore in FXSAVE/FXRSTOR opcodes 2003-01-23 17:53:11 +00:00
Christophe Bothamy
939b558fdf - apply patch.sysenterexit-mrieker:
- adds sysenter/sysexit support for cpu-level>=6
  - enabled by ./configure --enable-sep
2003-01-20 20:10:31 +00:00
Peter Tattam
24d4a5003c patches to CPUID required to get latest x86-64 linux kernel (2.4.20) to run.
I believe this patch is ok, however it should be regression tested to make sure
nothing is broken.
2003-01-14 07:46:05 +00:00
Peter Tattam
6e359d62ed disable calling external debugger when jumping in & out of 64 bit mode. 2003-01-14 07:40:21 +00:00
Stanislav Shwartsman
5803e20240 Changed policy of SSE/SSE2 checking 2002-11-13 21:00:05 +00:00
Stanislav Shwartsman
3cd6f7282d Alloc setting OFXCSR (bit9) of CR4 in SSE/SSE2 enabled 2002-11-08 20:26:12 +00:00
Bryce Denney
4f53ba4e39 - bx_gui is now a pointer, so it needs to be 'bx_gui->' not 'bx_gui.' 2002-10-27 22:26:34 +00:00
Bryce Denney
cec9135e9f - Apply patch.replace-Boolean rev 1.3. Every "Boolean" is now changed to a
"bx_bool" which is always defined as Bit32u on all platforms.  In Carbon
  specific code, Boolean is still used because the Carbon header files
  define it to unsigned char.
- this fixes bug [ 623152 ] MacOSX: Triple Exception Booting win95.
  The bug was that some code in Bochs depends on Boolean to be a
  32 bit value.  (This should be fixed, but I don't know all the places
  where it needs to be fixed yet.)  Because Carbon defined Boolean as
  an unsigned char, Bochs just followed along and used the unsigned char
  definition to avoid compile problems.  This exposed the dependency
  on 32 bit Boolean on MacOS X only and led to major simulation problems,
  that could only be reproduced and debugged on that platform.
- On the mailing list we debated whether to make all Booleans into "bool" or
  our own type.  I chose bx_bool for several reasons.
  1. Unlike C++'s bool, we can guarantee that bx_bool is the same size on all
     platforms, which makes it much less likely to have more platform-specific
     simulation differences in the future.  (I spent hours on a borrowed
     MacOSX machine chasing bug 618388 before discovering that different sized
     Booleans were the problem, and I don't want to repeat that.)
  2. We still have at least one dependency on 32 bit Booleans which must be
     fixed some time, but I don't want to risk introducing new bugs into the
     simulation just before the 2.0 release.

Modified Files:
    bochs.h config.h.in gdbstub.cc logio.cc main.cc pc_system.cc
    pc_system.h plugin.cc plugin.h bios/rombios.c cpu/apic.cc
    cpu/arith16.cc cpu/arith32.cc cpu/arith64.cc cpu/arith8.cc
    cpu/cpu.cc cpu/cpu.h cpu/ctrl_xfer16.cc cpu/ctrl_xfer32.cc
    cpu/ctrl_xfer64.cc cpu/data_xfer16.cc cpu/data_xfer32.cc
    cpu/data_xfer64.cc cpu/debugstuff.cc cpu/exception.cc
    cpu/fetchdecode.cc cpu/flag_ctrl_pro.cc cpu/init.cc
    cpu/io_pro.cc cpu/lazy_flags.cc cpu/lazy_flags.h cpu/mult16.cc
    cpu/mult32.cc cpu/mult64.cc cpu/mult8.cc cpu/paging.cc
    cpu/proc_ctrl.cc cpu/segment_ctrl_pro.cc cpu/stack_pro.cc
    cpu/tasking.cc debug/dbg_main.cc debug/debug.h debug/sim2.cc
    disasm/dis_decode.cc disasm/disasm.h doc/docbook/Makefile
    docs-html/cosimulation.html fpu/wmFPUemu_glue.cc
    gui/amigaos.cc gui/beos.cc gui/carbon.cc gui/gui.cc gui/gui.h
    gui/keymap.cc gui/keymap.h gui/macintosh.cc gui/nogui.cc
    gui/rfb.cc gui/sdl.cc gui/siminterface.cc gui/siminterface.h
    gui/term.cc gui/win32.cc gui/wx.cc gui/wxmain.cc gui/wxmain.h
    gui/x.cc instrument/example0/instrument.cc
    instrument/example0/instrument.h
    instrument/example1/instrument.cc
    instrument/example1/instrument.h
    instrument/stubs/instrument.cc instrument/stubs/instrument.h
    iodev/cdrom.cc iodev/cdrom.h iodev/cdrom_osx.cc iodev/cmos.cc
    iodev/devices.cc iodev/dma.cc iodev/dma.h iodev/eth_arpback.cc
    iodev/eth_packetmaker.cc iodev/eth_packetmaker.h
    iodev/floppy.cc iodev/floppy.h iodev/guest2host.h
    iodev/harddrv.cc iodev/harddrv.h iodev/ioapic.cc
    iodev/ioapic.h iodev/iodebug.cc iodev/iodev.h
    iodev/keyboard.cc iodev/keyboard.h iodev/ne2k.h
    iodev/parallel.h iodev/pci.cc iodev/pci.h iodev/pic.h
    iodev/pit.cc iodev/pit.h iodev/pit_wrap.cc iodev/pit_wrap.h
    iodev/sb16.cc iodev/sb16.h iodev/serial.cc iodev/serial.h
    iodev/vga.cc iodev/vga.h memory/memory.h memory/misc_mem.cc
2002-10-25 11:44:41 +00:00
Bryce Denney
5e520261db Add plugin support to Bochs by merging all the changes from the
BRANCH_PLUGINS branch!

Authors:
  Bryce Denney
  Christophe Bothamy
  Kevin Lawton (we grabbed a lot of plugin code from plex86)
Testing help from:
  Volker Ruppert
  Don Becker (Psyon)
  Jeremy Parsons (Br'fin)

The change log is too long to paste in here.  To read the change log, do
  cvs log patches/patch.final-from-BRANCH_PLUGINS.gz

All the changes and a detailed description are contained in a patch
called patch.final-from-BRANCH_PLUGINS.gz.  To look at the complete
patch, do
  cvs upd -r1.1 patches/patch.final-from-BRANCH_PLUGINS.gz

Then you will have a local copy of the patch, which you can gunzip and
play with however you want.

Modified Files:
    .bochsrc Makefile.in aclocal.m4 bochs.h config.h.in configure
    configure.in gdbstub.cc logio.cc main.cc pc_system.cc
    pc_system.h state_file.h bios/Makefile.in bios/rombios.c
    cpu/Makefile.in cpu/access.cc cpu/apic.cc cpu/arith16.cc
    cpu/arith32.cc cpu/arith8.cc cpu/cpu.cc cpu/cpu.h
    cpu/ctrl_xfer32.cc cpu/exception.cc cpu/fetchdecode.cc
    cpu/fetchdecode64.cc cpu/flag_ctrl.cc cpu/flag_ctrl_pro.cc
    cpu/init.cc cpu/io.cc cpu/logical16.cc cpu/logical32.cc
    cpu/logical8.cc cpu/paging.cc cpu/proc_ctrl.cc
    cpu/protect_ctrl.cc cpu/segment_ctrl_pro.cc cpu/shift16.cc
    cpu/shift32.cc cpu/stack64.cc cpu/string.cc cpu/tasking.cc
    debug/Makefile.in debug/dbg_main.cc disasm/Makefile.in
    doc/docbook/user/user.dbk dynamic/Makefile.in fpu/Makefile.in
    gui/Makefile.in gui/amigaos.cc gui/beos.cc gui/carbon.cc
    gui/control.cc gui/control.h gui/gui.cc gui/gui.h
    gui/keymap.cc gui/keymap.h gui/macintosh.cc gui/nogui.cc
    gui/rfb.cc gui/sdl.cc gui/sdlkeys.h gui/siminterface.cc
    gui/siminterface.h gui/term.cc gui/win32.cc gui/wx.cc
    gui/wxdialog.cc gui/wxdialog.h gui/wxmain.cc gui/wxmain.h
    gui/x.cc gui/keymaps/sdl-pc-de.map gui/keymaps/sdl-pc-us.map
    gui/keymaps/x11-pc-de.map instrument/example0/instrument.h
    instrument/example1/instrument.h
    instrument/stubs/instrument.cc instrument/stubs/instrument.h
    iodev/Makefile.in iodev/biosdev.cc iodev/biosdev.h
    iodev/cdrom.cc iodev/cmos.cc iodev/cmos.h iodev/devices.cc
    iodev/dma.cc iodev/dma.h iodev/eth_fbsd.cc iodev/eth_linux.cc
    iodev/eth_null.cc iodev/eth_tap.cc iodev/floppy.cc
    iodev/floppy.h iodev/guest2host.cc iodev/guest2host.h
    iodev/harddrv.cc iodev/harddrv.h iodev/iodebug.cc
    iodev/iodebug.h iodev/iodev.h iodev/keyboard.cc
    iodev/keyboard.h iodev/ne2k.cc iodev/ne2k.h iodev/parallel.cc
    iodev/parallel.h iodev/pci.cc iodev/pci.h iodev/pci2isa.cc
    iodev/pci2isa.h iodev/pic.cc iodev/pic.h iodev/pit.cc
    iodev/pit.h iodev/pit_wrap.cc iodev/pit_wrap.h iodev/sb16.cc
    iodev/sb16.h iodev/scancodes.cc iodev/scancodes.h
    iodev/serial.cc iodev/serial.h iodev/slowdown_timer.cc
    iodev/slowdown_timer.h iodev/unmapped.cc iodev/unmapped.h
    iodev/vga.cc iodev/vga.h memory/Makefile.in memory/memory.cc
    memory/memory.h memory/misc_mem.cc misc/bximage.c
    misc/niclist.c
Added Files:
    README-plugins extplugin.h ltdl.c ltdl.h ltdlconf.h.in
    ltmain.sh plugin.cc plugin.h
2002-10-24 21:07:56 +00:00
Stanislav Shwartsman
466a3226f5 FXSAVE/FXRSTOR stubs defined in sse.cc 2002-10-19 21:47:28 +00:00
Stanislav Shwartsman
194952a53d Merged BOCHS-SSE branch 2002-10-16 17:37:35 +00:00
Peter Tattam
b968c4e5c8 Latest round of patches/fixups to get 64 bit emulation further.
This is an interim update to allow others to test.

We have userland code running!!! (up to a point)

Able to start executing "sash" as /sbin/init in userland from linux 64 bit
kernel until it crashes trying to access a null pointer.  No kernel panics
though, just a segfault loop.
2002-10-08 14:43:18 +00:00
Kevin Lawton
66452e9898 Replaced tabs in cpu/*.{cc,h} files with spaces. 2002-10-04 17:04:33 +00:00
Kevin Lawton
67721c48f4 The convience functions protected_mode(), v8086_mode() and real_mode()
now simply return a cached value which is set upon mode changes.
  The biggest problem was protected_mode() which did something like:

    return CR0.PM && ! EFLAGS.VM

  This adds up when it was being executed many times in branch functions
  etc.  Now, cached values are set and sampled instead.
2002-09-29 22:38:18 +00:00
Kevin Lawton
f99f17bca4 Integrated CPUID CMPXCHG8B bit setting patch from John_Bäckstrand.
Moved it slightly, but it is correct.
2002-09-29 16:23:03 +00:00
Kevin Lawton
13a1e55f20 Committed patches/patch-bochs-instrumentation from Stanislav.
Some things changed in the ctrl_xfer*.cc, fetchdecode*.cc,
and cpu.cc since the original patches, so I did some patch
integration by hand.  Check the placement of the
macros BX_INSTR_FETCH_DECODE_COMPLETED() and BX_INSTR_OPCODE()
in cpu.cc to make sure I go them right.  Also, I changed the
parameters to BX_INSTR_OPCODE() to update them to the new code.
I put some comments before each of these to help determine if
the placement is right.

These macros are only compiled in if you are gathering instrumentation
data from bochs, so they shouldn't effect others.
2002-09-28 00:54:05 +00:00
Peter Tattam
67082a5b50 Implemented SWAPGS instruction.
Note that it is unusual to decode (see SGDT instruction)
2002-09-25 14:09:08 +00:00
Bryce Denney
6e473648bd - remove extra #endifs that came from merging Peter's and Kevin's code 2002-09-24 13:57:37 +00:00
Bryce Denney
de0e58c2c5 These changes are from Peter Tattam
- fix load_ss, remove load_ss_null
- change the "#if KPL64Hacks" around msr stuff into "#if BX_IGNORE_BAD_MSR"
- remove "#if KPL64Hacks" from BX_CPU_C::can_push
- segment_ctrl_pro.cc: bug fix to ss == null handling in 64 bit mode

Modified: cpu/cpu.h cpu/ctrl_xfer_pro.cc cpu/exception.cc
cpu/proc_ctrl.cc cpu/segment_ctrl_pro.cc cpu/stack_pro.cc
2002-09-24 08:29:06 +00:00
Kevin Lawton
281e62d8b1 I integrated my hacks to get Linux/x86-64 booting. To keep
these from interfering from a normal compile here's what I did.
In config.h.in (which will generate config.h after a configure),
I added a #define called KPL64Hacks:

  #define KPL64Hacks

*After* running configure, you must set this by hand.  It will
default to off, so you won't get my hacks in a normal compile.
This will go away soon.  There is also a macro just after that
called BailBigRSP().  You don't need to enabled that, but you
can.  In many of the instructions which seemed like they could
be hit by the fetchdecode64() process, but which also touched
EIP/ESP, I inserted a macro.  Usually this macro expands to nothing.
If you like, you can enabled it, and it will panic if it finds
the upper bits of RIP/RSP set.   This helped me find bugs.

Also, I cleaned up the emulation in ctrl_xfer{8,16,32}.cc.
There were some really old legacy code snippets which directly
accessed operands on the stack with access_linear.  Lots of
ugly code instead of just pop_32() etc.  Cleaning those up,
minimized the number of instructions which directly manipulate
the stack pointer, which should help in refining 64-bit support.
2002-09-24 00:44:56 +00:00
Bryce Denney
00b2607e6a - added bit definitions of CR4 in comments 2002-09-23 14:45:44 +00:00
Bryce Denney
c9b05afa6d - add "Reserved" bitfields to comments, to make it more complete 2002-09-23 14:38:14 +00:00
Bryce Denney
8b1a27fc7e - I forgot to mention that the previous rev was a patch from Peter Tattam 2002-09-23 14:33:49 +00:00
Bryce Denney
185254e367 - for x86-64, claim that we are an "AuthenticAMD" processor
- return model=2 so that Linux recognizes the processor as having an APIC.
  We don't really know what Hammer returns.
- in SetCR4, allow bits 9 and 10 to be written
2002-09-23 14:31:21 +00:00
Kevin Lawton
402d02974d Moved the EFLAGS.RF check and clearing of inhibit_mask code
in cpu.cc out of the main loop, and into the asynchronous
events handling.  I went through all the code paths, and
there doesn't seem to be any reason for that code to be
in the hot loop.

Added another accessor for getting instruction data, called
modC0().  A lot of instructions test whether the mod field
of mod-nnn-rm is 0xc0 or not, ie., it's a register operation
and not memory.  So I flag this in fetchdecode{,64}.cc.
This added on the order of 1% performance improvement for
a Win95 boot.

Macroized a few leftover calls to Write_RMV_virtual_xyz()
that didn't get modified in the x86-64 merge.  Really, they
just call the real function for now, but I want to have them
available to do direct writes with the guest2host TLB pointers.
2002-09-20 03:52:59 +00:00
Kevin Lawton
4e51dcae40 Converted all the remaining available separate fields in bxInstruction_c
to bitfields.  bxInstruction_c is now 24 bytes, including 4 for
the memory addr resolution function pointer, and 4 for the
execution function pointer (16 + 4 + 4).

Coded more accessors, to abstract access from most code.
2002-09-18 08:00:43 +00:00
Kevin Lawton
6723ca9bf4 Moved more separate fields in the bxInstruction_c into bitfields
with accessors.  Had to touch a number of files to update the
access using the new accessors.

Moved rm_addr to the CPU structure, to slim down bxInstruction_c
and to prevent future instruction caching from getting sprayed
with writes to individual rm_addr fields.  There only needs to
be one.  Though need to deal with instructions which have
static non-modrm addresses, but which are using rm_addr since
that will change.

bxInstruction_c is down to about 40 bytes now.  Trying to
get down to 24 bytes.
2002-09-18 05:36:48 +00:00
Kevin Lawton
07b0df2a8a Updated accessing of modrm/sib addressing information to
use accessors.  This lets me work on compressing the
size of fetch-decode structure (now called bxInstruction_c).

I've reduced it down to about 76 bytes.  We should be able
to do much better soon.  I needed the abstraction of the
accessors, so I have a lot of freedom to re-arrange things
without making massive future changes.

Lost a few percent of performance in these mods, but my
main focus was to get the abstraction.
2002-09-17 22:50:53 +00:00
Bryce Denney
f1a3e0307a - add #if BX_CPU_LEVEL>=4 around cr0.wp and cr4 so that i386 will compile 2002-09-17 22:14:33 +00:00
Kevin Lawton
80dd7a07ec Removed references to building libextdb.a. It doesn't seem to
be used at all, and Peter didn't want it.  "extdb.o" is compiled
into libcpu.a, if configured for it.

Removed a few #warnings for x86-64 compile, based on Peter's
line-item comments regarding the warnings I inserted during
the port/merge.
2002-09-15 15:10:21 +00:00
Kevin Lawton
278e27d5fe Merged proc_ctrl.cc. Also fixed a bug in CR4 reloading; we were
printing a message when a reserved bit was set, but not causing
a #GP(0).  As well, I force a new PAE support option to 1 when
Hammer support is enabled.
2002-09-14 23:17:55 +00:00
Kevin Lawton
93d05990cc Updated CR4 to use the patented Bryce bitfields accessor method for
both cpu32 and cpu64, to make upcoming merging easier, and the
code cleaner.  Compiled for debug as well, and fixed CR4 for that
also.
2002-09-14 19:21:41 +00:00
Kevin Lawton
6655634179 I merged the cpu/cpu.h and cpu64/cpu.h files as well as the
other header files.  There no longer are any *.h files in cpu64/.
Had to make some changes to the *.cc files for dealing with
accesses to eip.
2002-09-13 00:15:23 +00:00
Bryce Denney
5fc31bcfda - this revision changes the way eflags are accessed throughout the cpu and
cpu64 directories.  Instead of using the macros introduced in cpu.h rev 1.37
  such as GetEFlagsDFLogical and SetEFlagsDF and ClearEFlagsDF, I made inline
  methods on the BX_CPU_C object that access the eflags fields.  The problem
  with the macros is that they cannot be used outside the BX_CPU_C object.  The
  macros have now been removed, and all references to eflags now use these new
  accessors.
- I debated whether to put the accessors as members of the BX_CPU_C object
  or members of the bx_flags_reg_t struct.  I chose to make them members
  of BX_CPU_C for two reasons: 1. the lazy flags are implemented as
  members of BX_CPU_C, and 2. the eflags are referenced in many many places
  and it is more compact without having to put eflags in front of each.  (The
  real problem with compactness is having to write BX_CPU_THIS_PTR in front of
  everything, but that's another story.)
- Kevin pointed out a major bug in my set accessor code.  What a difference a
  little tilde can make!  That is fixed now.
- modified: load32bitOShack.cc debug/dbg_main.cc
  and in both cpu and cpu64 directories:
    cpu.cc cpu.h ctrl_xfer_pro.cc debugstuff.cc exception.cc flag_ctrl.cc
    flag_ctrl_pro.cc init.cc io.cc io_pro.cc proc_ctrl.cc soft_int.cc
    string.cc vm8086.cc
2002-09-12 18:10:46 +00:00
Kevin Lawton
08576b24be I implemented Global pages. Though, I haven't tested them. :^)
You need to use '--enable-global-pages' to configure in support.
If you have something to boot that uses them, give them a
spin.  Really the were introduced for PPro and above, but
I haven't put in any limits.  CPUID and CR4 report the proper
bits when configured, regardless of --enable-cpu-level at the
moment.
2002-09-10 03:52:32 +00:00
Bryce Denney
be659a09b3 - check in Stanislav Shwartsman's patch "bochs-mmx.patch-endian-support".
He writes: Detailed description: MMX instruction set support.
  Also supports BIG_ENDIAN systems. Tested on Solaris and HP1100.
- modified files:
    configure.in cpu/Makefile.in cpu/cpu.h cpu/fetchdecode.cc
    cpu/proc_ctrl.cc fpu/fpu_system.h fpu/wmFPUemu_glue.cc
- added files: cpu/i387.h cpu/mmx.cc
2002-09-09 16:11:25 +00:00
Kevin Lawton
0d7a5fdf3c I rehashed the way the EFLAGS register was stored internally.
All the EFLAGS bits used to be cached in separate fields.  I left
a few of them in separate fields for now - might remove them
at some point also.  When the arithmetic fields are known
(ie they're not in lazy mode), they are all cached in a
32-bit EFLAGS image, just like the x86 EFLAGS register expects.
All other eflags are store in the 32-bit register also, with
a few also mirrored in separate fields for now.

The reason I did this, was so that on x86 hosts, asm() statements
can be #ifdef'd in to do the calculation and get the native
eflags results very cheaply.  Just to test that it works, I
coded ADD_EdId() and ADD_EwIw() with some conditionally compiled
asm()s for accelerated eflags processing and it works.

-Kevin
2002-09-08 04:08:14 +00:00
Kevin Lawton
51c93e12a1 The paging unit gets notified of all CR0/CR3/CR4 updates so
it can decide how to proceed.  Some of those bits are necessary
to make TLB invalidation decisions.  INVLPG doesn't cause
a whole TLB flush anymore, just one page.  Some of the
current CPU behaviours model the P6, especially on CR0
reloads.  Earlier processors kept some pre-change pre-fetched
instructions until a branch.  We could probably model that
by setting a flag, and letting the revalidate_prefetch_q
function cause serialization.

The TLB flush code only invalidates entries which are not
already invalidated for the case where the TLB invalidation
ID trick is not in use.
2002-09-07 05:21:28 +00:00
Kevin Lawton
f0c9896964 Now, when you compile with --enable-guest2host-tlb, non-paged
mode uses the notion of the guest-to-host TLB.  This has the
benefit of allowing more uniform and streamlined acceleration
code in access.cc which does not have to check if CR0.PG
is set, eliminating a few instructions per guest access.
Shaved just a little off execution time, as expected.

Also, access_linear now breaks accesses which span two pages,
into two calls the the physical memory routines, when paging
is off, just like it always has for paging on.  Besides
being more uniform, this allows the physical memory access
routines to known the complete data item is contained
within a single physical page, and stop reapplying the
A20ADDR() macro to pointers as it increments them.
Perhaps things can be optimized a little more now there too...
I renamed the routines to {read,write}PhysicalPage() as
a reminder that these routines now operate on data
solely within one page.

I also added a little code so that the paging module is
notified when the A20 line is tweaked, so it can dump
whatever mappings it wants to.
2002-09-05 02:31:24 +00:00
Kevin Lawton
d07c1c0bb0 I rehashed the way the paging code stores protection bits,
so that a compare of the current access could be done more
efficiently against the cached values, both in the normal
paging routines, and in the accelerated code in access.cc.

This cut down the amount of code path needed to get to
direct use of a host address nicely, and speed definitely
got a boost as a result, especially if you use the
--enable-guest2host-tlb option.

The CR0.WP flag was a real pain, because it imparts
a complication on the way protections work.  Fortunately
it's not a high-change flag, so I just base the new
cached info on the current CR0.WP value, and dump
the TLB cache when it changes.
2002-09-04 08:59:13 +00:00
Kevin Lawton
3a5f338419 Integrated patches for:
- Paging code rehash.  You must now use --enable-4meg-pages to
    use 4Meg pages, with the default of disabled, since we don't well
    support 4Meg pages yet.  Paging table walks model a real CPU
    more closely now, and I fixed some bugs in the old logic.
  - Segment check redundancy elimination.  After a segment is loaded,
    reads and writes are marked when a segment type check succeeds, and
    they are skipped thereafter, when possible.
  - Repeated IO and memory string copy acceleration.  Only some variants
    of instructions are available on all platforms, word and dword
    variants only on x86 for the moment due to alignment and endian issues.
    This is compiled in currently with no option - I should add a configure
    option.
  - Added a guest linear address to host TLB.  Actually, I just stick
    the host address (mem.vector[addr] address) in the upper 29 bits
    of the field 'combined_access' since they are unused.  Convenient
    for now.  I'm only storing page frame addresses.  This was the
    simplest for of such a TLB.  We can likely enhance this.  Also,
    I only accelerated the normal read/write routines in access.cc.
    Could also modify the read-modify-write versions too.  You must
    use --enable-guest2host-tlb, to try this out.  Currently speeds
    up Win95 boot time by about 3.5% for me.  More ground to cover...
  - Minor mods to CPUI/MOV_CdRd for CMOV.
  - Integrated enhancements from Volker to getHostMemAddr() for PCI
    being enabled.
2002-09-01 20:12:09 +00:00
Kevin Lawton
d52b23daf1 Made some very minor mods, to make CPUID aware of CMOV instructions
for BX_CPU_LEVEL >= 6, and to have the CMOV instructions generate
an undefined opcode exception after printing info that they were
called, if BX_CPU_LEVEL <= 5.  I suppose we could have a separate
configure option, but mirroring Intel, CMOV is available as of
Pentium Pro.

For now, you have to compile with --enable-cpu-level=6 for CMOV
support to be compiled in.
2002-09-01 04:01:14 +00:00
Christophe Bothamy
17adce9633 - added MOV_CdRd in v8086 mode (from Martin Str|mberg) 2002-08-10 12:06:26 +00:00
Christophe Bothamy
1f577b31fa - ouput unknown MSR regsiter number 2002-08-01 07:23:11 +00:00
Bryce Denney
1403a59ec4 - apply patch from Zwane Mwaikambo <zwane@linuxpower.ca> posted to
mailing list.
2002-07-25 13:30:07 +00:00
Bryce Denney
7e04c23d2f - check in Mike Reiker's 4meg page code from a patch that he submitted last
November 17.
2002-06-19 15:49:07 +00:00
instinc
1e7cc13b04 reversed the changes done to exception() 2002-04-11 01:19:24 +00:00
instinc
01b699af16 as per bug report 498386, line 550 was causing a panic which has been disabled 2002-04-11 00:36:02 +00:00
Bryce Denney
49decc485c - when merging EDX and EAX to create the apic base address, add
a typecast to Bit64u before shifting left by 32.  Otherwise
  the EDX<<32 would overflow on 32 bit machines and the address would
  be wrong.
2002-04-03 15:12:22 +00:00
Bryce Denney
640d71d017 - check in Zwane Mwaikambo's MSR patch: patch.msr. 2002-03-27 16:04:05 +00:00
Bryce Denney
976e0b67d9 - clarify panic message. It panics if HLT is executed from segment 0xf000,
in other words from ROM BIOS code.
2001-11-18 16:32:40 +00:00
Bryce Denney
e0b4801b1f - commit Roland Mainz's idle hack as a configure option. To try it,
configure with --enable-idle-hack.  I have moved most of the code into
  x.cc since it is X windows specific.
2001-11-12 00:45:09 +00:00
Bryce Denney
b86dbe1f3c - committed patches/patch.no-busy-in-tr-cache. I'm leaving the patch
lying around for a while in case it needs to be reverted.
2001-10-09 21:15:14 +00:00
Bryce Denney
daf2a9fb55 - add RCS Id to header of every file. This makes it easier to know what's
going on when someone sends in a modified file.
2001-10-03 13:10:38 +00:00
Bryce Denney
4073d65f4d - apply patch [ #455014 ] CR0 bug in 80486, described as:
> In the register CR0, when the bit PM is enabled, the bit 4 is 0
  > when should be 1.
  Another fix from an anonymous donor.
2001-09-19 17:36:54 +00:00
Todd T.Fries
cd9733391b AtheOS triggers this, move to debug 2001-08-24 21:02:37 +00:00
Todd T.Fries
2bbb1ef8eb strip '\n' from BX_{INFO,DEBUG,ERROR,PANIC}
don't need it, moved the output of it into the general io functions.
saves space, as well as removes the confusing output if a '\n' is left off
2001-05-30 18:56:02 +00:00
Todd T.Fries
e291dd17d4 demote BX_INFO to BX_ERROR 2001-05-25 22:17:51 +00:00
Bryce Denney
49664f7503 - parts of the SMP merge apparantly broke the debugger and this revision
tries to fix it.  The shortcuts to register names such as AX and DL are
  #defines in cpu/cpu.h, and they are defined in terms of BX_CPU_THIS_PTR.
  When BX_USE_CPU_SMF=1, this works fine.  (This is what bochs used for
  a long time, and nobody used the SMF=0 mode at all.)  To make SMP bochs
  work, I had to get SMF=0 mode working for the CPU so that there could
  be an array of cpus.

  When SMF=0 for the CPU, BX_CPU_THIS_PTR is defined to be "this->" which
  only works within methods of BX_CPU_C.  Code outside of BX_CPU_C must
  reference BX_CPU(num) instead.
- to try to enforce the correct use of AL/AX/DL/etc. shortcuts, they are
  now only #defined when "NEED_CPU_REG_SHORTCUTS" is #defined.  This is
  only done in the cpu/*.cc code.
2001-05-24 18:46:34 +00:00
Bryce Denney
26cf93f455 - fixed stupid bug in my RDTSC code, which made the TSD bit
(time stamp disable) not work correctly
2001-05-24 18:03:14 +00:00
Bryce Denney
3503104390 - configure turns on APIC when cpu level > 5
- now the APIC feature bit is really controlled by cpu level and
  BX_APIC_SUPPORT, so it won't go on at the wrong time.
2001-05-23 15:54:05 +00:00
Bryce Denney
e61d00351f - merged BRANCH-smp-bochs into main branch. For details see comments
in BRANCH-smp-bochs revisions.
- The general task was to make multiple CPU's which communicate
  through their APICs.  So instead of BX_CPU and BX_MEM, we now have
  BX_CPU(x) and BX_MEM(y).  For an SMP simulation you have several
  processors in a shared memory space, so there might be processors
  BX_CPU(0..3) but only one memory space BX_MEM(0).  For cosimulation,
  you could have BX_CPU(0) with BX_MEM(0), then BX_CPU(1) with
  BX_MEM(1).  WARNING: Cosimulation is almost certainly broken by the
  SMP changes.
- to simulate multiple CPUs, you have to give each CPU time to execute
  in turn.  This is currently implemented using debugger guards.  The
  cpu loop steps one CPU for a few instructions, then steps the
  next CPU for a few instructions, etc.
- there is some limited support in the debugger for two CPUs, for
  example printing information from each CPU when single stepping.
2001-05-23 08:16:07 +00:00
Todd T.Fries
a628039f5f report undefined opcode if not implemented instead of panicing for RDTSC 2001-05-16 17:27:01 +00:00
Todd T.Fries
3c7414a418 error and undefined opcode + typo with BX_INFO in code only used on i386's 2001-05-16 16:50:04 +00:00
Todd T.Fries
bdb89cd364 merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.

In general this provides a generic interface for logging.

logfunctions:: is a class that is inherited by some classes, and also
.   allocated as a standalone global called 'genlog'.  All logging uses
.   one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
.   class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
.   respectively.
.
.   An example usage:
.     BX_INFO(("Hello, World!\n"));

iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance.  It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf().  At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.

More cleanup is coming, but this works for now.  If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.

Comments, bugs, flames, to me: todd@fries.net
2001-05-15 14:49:57 +00:00
Bryce Denney
a6fef54678 - update copyright dates to 2001 for all mandrake headers
- for bochs files with other header, replaced with current mandrake header
2001-04-10 02:20:02 +00:00
cvs
beff63eb32 - entered original Bochs snapshot bochs-2000_0325a.tar.gz from
ftp.bochs.com
2001-04-10 01:04:59 +00:00